hsp43216 Intersil Corporation, hsp43216 Datasheet
hsp43216
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hsp43216 Summary of contents
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... Data Sheet Halfband Filter The HSP43216 Halfband Filter addresses a wide variety of applications by combining sample frequency quadrature up/down convert circuitry with a fixed coefficient halfband filter processor as shown in the block diagram. These elements may be configured to operate in one of the four following modes: decimate by 2 filtering of a real input signal ...
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... BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 HSP43216 67-TAP QUADRATURE HALFBAND DOWN FILTER CONVERT PROCESSOR PROCESSOR HSP43216JC (100 LD MQFP) TOP VIEW 100 ...
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... AOUT15 and BOUT15-bits are inverted from the normal two’s complement representation. AOUT0-15 O Output Bus A. AOUT0 is the LSB. BOUT0-15 O Output Bus B. BOUT0 is the LSB. 3 HSP43216 HSP43216 (84 LD PLCC) TOP VIEW ...
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... INT/EXT RND0-2 FMT USB/LSB Functional Description The operation of the HSP43216 centers around a fixed coefficient, 67-Tap, Halfband Filter Processor as shown in Figure 1. The Halfband Filter Processor operates stand alone to provide two fundamental modes of operation: interpolate or decimate by two filtering of a real signal. In two other modes, the Quadrature Up/Down Convert circuitry ...
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... MODE Decimate by Two Interpolate by Two Down Convert and Decimate Quadrature to Real 5 HSP43216 The polyphase implementation of the halfband filter provides the flexibility to realize a variety of filter /4 spectral shift on configurations. In Decimate by Two Mode, the outputs of S the each polyphase branch are summed to yield the filter output ...
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TABLE 3. FREQUENCY RESPONSE OF THE 67-TAP HALFBAND FILTER NORMALIZED TO THE MODE SPECIFIC SAMPLE RATE FREQUENCY MAGNITUDE FREQUENCY (NORMALIZED) (dB) (NORMALIZED) 0.000000 -0.000256 0.125000 0.003906 -0.000143 0.128906 0.007812 -0.000071 0.132812 0.011719 -0.000013 0.136719 0.015625 -0.000004 0.140625 0.019531 -0.000001 0.144531 ...
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... Output Flow Controller to yield the real output sample stream. The SYNC control input may be used to align the zero degree phase of 7 HSP43216 the Up Convert LO with a particular input sample as described in the Operational Modes Section. The Up Convert Processor also scales the data streams output from the Filter Processor as required by the operational mode ...
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... Odd Tap Filter reduces to a delay and multiply operation. The operation of the HSP43216 in Decimate by Two mode is analogous to the polyphase implementation in Figure 6. In this mode, the internal data paths are routed as shown in Figure 7A and Figure 7B ...
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... CLK rate of the device (104 MSPS). With external multiplexing, the minimum pipeline delay through the upper processing leg is 9 CLK’s and the pipeline delay through the lower processing leg is 26 CLK’s as shown in Figure 7B HSP43216 † PIPELINE DELAY 2-35 † GROUP DELAY 19 † ...
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... Decimate by Two example, the even or odd tap filters are comprised of the even or odd indexed coefficients from the original transversal filter. The operation of the HSP43216 in Interpolate by Two mode is analogous to the polyphase example above. In this mode the internal data flow is routed as shown in Figure 11A and Figure 11B ...
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... The Down Convert and Decimate mode is most easily understood by first considering the transversal implementation using a 7 tap filter as shown in Figure 13. 11 HSP43216 By examining the combination of down conversion, filtering and decimation seen that the real outputs are only dependent on the sum-of-products for the even indexed ...
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... I2 = -X5(C1)+X7(C3)-X9(C5) FIGURE 14. DOWN CONVERT AND DECIMATE FUNCTION USING POLYPHASE FILTERS 12 HSP43216 The HSP43216’s implementation of Down Convert and Decimate mode is analogous to the polyphase solution shown in Figure 14. The part’s data flow diagram for this ...,R2,R0 2 mode is shown in Figure 15A and Figure 15B. As seen in ...
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... Figure 17. NOTE: For proper operation, the samples demultiplexed to the AIN0-15 input must precede those input to the BIN0-15 input in sample order. For example, given a data sequence x0, x1, x2, and x3, 13 HSP43216 † PIPELINE DELAY 2-35 † GROUP DELAY 19 † ...
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... Real Conversion mode is shown in Figure 20. In this implementation, the real and imaginary components of a complex input stream drive the even and odd tap filters. The output of each filter is then modulated by the non-zero mix factors and multiplexed into a single real output stream. 14 HSP43216 ..R1, ..I1,I0 Y(0) = 0(0(C0)+R0(C1)+0(C2)+R1(C3)+0(C4)+R2(C5)+0(C6))+ ’ ...
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... G G FIGURE 21B. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL CONVERSION MODE (INT/EXT = the other modes, the operation of the HSP43216 in Quadrature to real Conversion mode is analogous to that of the polyphase solution described above. The data flow diagrams for this particular mode are shown in Figures 21A and 21B ...
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... L 5. Not tested, but characterized at initial design and at major process/design changes. 6. Maximum junction temperature must be considered when operating part at high clock frequencies. 16 HSP43216 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V PLCC Package MQFP Package . . . . . . . . . . . . . . . . . . ...
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... Test V = 3.0V 4.0V 0V. IH IHC IL 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. 17 HSP43216 SYMBOL ...
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... Waveforms CLK AIN0-15, BIN-15 MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB AOUT0-15, BOUT0-15 OE 2.0V 0.8V 18 HSP43216 FIGURE 23. TIMING RELATIVE TO CLK t r FIGURE 24. OUTPUT RISE AND FALL TIMES FN3365.9 April 18, 2007 ...
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... E1 include mold mismatch and are measured at the extreme material condition at the body parting line measured at seating plane -C- 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 19 HSP43216 N84.1.15 0.004 (0.10 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.025 (0.64) R ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 HSP43216 Q100.14x20 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...