hsp43216 Intersil Corporation, hsp43216 Datasheet - Page 9

• Manufacturer Part Number: hsp43216
• Description: Halfband Filter
• Manufacturer: Intersil Corporation

If internal multiplexing is selected (INT/EXT = 1), the input data
stream is decomposed into even and odd samples internally by
the processing elements operating at one half of the input CLK
(see elements marked by “ † ” in Figure 7A). In this mode, the
Data Flow Controller routes data samples input through AIN0-
15 to upper and lower processing legs with a one sample
relative delay. Since a new data sample is clocked into either of
the processing legs at CLK/2, each leg processes a data
stream comprised of every other input sample, and the one
sample relative delay of each leg’s input forces the even
samples to be clocked into one leg while the odd samples are
clocked into the other. The user may choose which sample gets
routed to the upper (even) processing leg by asserting SYNC.
Specifically, a sample input on the CLK following the assertion
of SYNC will be routed to the upper processing leg as shown in
Figure 8. With internal multiplexing, the minimum pipeline delay
on the upper processing leg is 14 CLK’s and the pipeline delay
on the bottom leg is 47 CLK’s. The filtered and decimated data
stream is held on AOUT0-15 for 2 CLK’s.
If external multiplexing is selected (INT/EXT = 0), a
demultiplex function is required off chip to break the input
data into even and odd sample streams for input through
AIN0-15 and BIN0-15. In this mode, the Data Flow Controller
routes the even and odd sample streams directly to the
following processing elements which are all running at the
input CLK rate. This allows the device to perform decimate
by two filtering on signals sampled at up to twice the
maximum CLK rate of the device (104 MSPS). With external
multiplexing, the minimum pipeline delay through the upper
processing leg is 9 CLK’s and the pipeline delay through the
lower processing leg is 26 CLK’s as shown in Figure 7B. In
†
AIN0-15
AIN0-15
BIN0-15
Clocked at CLK/2
R
E
G
R
E
G
R
E
G
R
G
E
R
E
G
R
E
G
FIGURE 7B. DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INT/EXT = 0)
FIGURE 7A.
G
R
E
R
E
G
R
E
G
†
†
R
E
G
9
1
DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INT/EXT = 1)
1
1
1
R
E
G
R
E
G
†
R
E
G
†
R
E
G
†
PIPELINE DELAY 2-35
†
PIPELINE DELAY 19
†
†
PIPELINE DELAY 2-35
GROUP DELAY 19
GROUP DELAY 19
PIPELINE DELAY 19
GROUP DELAY 19
GROUP DELAY 19
EVEN TAP
EVEN TAP
ODD TAP
ODD TAP
FILTER
FILTER
FILTER
FILTER
HSP43216
this mode, SYNC has no effect on part operation.
NOTE: For proper operation, the samples demultiplexed
to the AIN0-15 input must precede those input to the
BIN0-15 input in sample order. For example, given a data
sequence x0, x1, x2 and x3, the demultiplex function would
route x0 and x2 to AIN0-15 and x1 and x3 to BIN0-15.
Interpolate By 2 Filter Mode (Mode1-0 = 01)
As with the Decimate by Two mode the concept of operation
for the Interpolate by Two Filter mode is more easily
understood by comparing a 7 tap transversal filter
implementation to the equivalent polyphase implementation.
The transversal implementation is shown in Figure 9.
By inspecting filter outputs in Figure 9, it is seen that the
even indexed outputs are the result of the sum-of-products
for the odd coefficients, and the odd indexed outputs are the
result of the sum-of-products for the even coefficients. This
computational partitioning is evident in the polyphase
implementation shown in Figure 10.
INPUTS DESIGNATED AS EVEN ARE PROCESSED ON THE UPPER
LEG, INPUTS DESIGNATED AS ODD ARE PROCESSED ON THE
LOWER LEG.
AIN0-15
FIGURE 8. DATA SYNCHRONIZATION WITH PROCESSING
SYNC
CLK
1
1
1
1
LEGS (INT/EXT = 1)
R
E
G
R
E
G
†
†
R
E
G
R
E
G
+
+
0
EVEN
R
N
D
R
N
D
1
M
F
T
M
F
T
R
E
G
ODD
R
E
G
R
E
G
R
E
G
AOUT0-15
AOUT0-15
OEA
OEA
2
EVEN
April 18, 2007
FN3365.9