pcf8523u/12aa/1 NXP Semiconductors, pcf8523u/12aa/1 Datasheet
pcf8523u/12aa/1
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pcf8523u/12aa/1 Summary of contents
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PCF8523 Real-Time Clock (RTC) and calendar Rev. 2 — 27 January 2011 1. General description The PCF8523 is a CMOS consumption. Data is transferred serially via an I 1000 kbit/s. Alarm and timer functions are available with the possibility to ...
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... PCF8523TK/1 PCF8523U/12AA/1 [1] Delivery form: sawn 6-inch wafer (see for 8-inch wafer (see 5. Marking Table 2. Type number PCF8523T/1 PCF8523TS/1 PCF8523TK/1 PCF8523U/12AA/1 PCF8523 Product data sheet Ordering information Package Name Description SO8 plastic small outline package; 8 leads; body width 3.9 mm TSSOP14 plastic thin shrink small outline package; 14 leads; ...
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... NXP Semiconductors 6. Block diagram OSCI C OSCI OSCILLATOR 32.768 kHz OSCO C OSCO V DD BATTERY BACKUP V BAT SWITCH-OVER CIRCUTRY V SS POWER-ON RESET 2 I C-BUS SDA INTERFACE SCL Fig 1. Block diagram of PCF8523 PCF8523 Product data sheet DIVIDER CLOCK CALIBRATION OFFSET SYSTEM CONTROL REAL-TIME CLOCK ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Fig 3. Fig 4. PCF8523 Product data sheet 1 OSCI OSCO 2 PCF8523T 3 V BAT Top view. For mechanical details, see Pin configuration for SO8 (PCF8523T) OSCI 1 OSCO 2 n.c. 3 PCF8523TS 4 V BAT n.c. 6 INT2 7 Top view. For mechanical details, see ...
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... NXP Semiconductors Fig 5. 7.2 Pin description Table 3. Pin description Symbol Pin SO8 TSSOP14 (PCF8523T) (PCF8523TS) OSCI 1 1 OSCO BAT INT2 - 7 CLKOUT - 8 SDA 5 10 SCL 6 11 INT1/CLKOUT [1] Wire length between quartz and package should be minimized. ...
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... NXP Semiconductors 8. Functional description The PCF8523 contains • 20 8-bit registers with an auto-incrementing address register, • An on-chip 32.768 kHz oscillator with two integrated load capacitors, • A frequency divider, which provides the source clock for the Real-Time Clock (RTC), • A programmable clock output, • ...
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... NXP Semiconductors 8.1 Register overview The 20 registers of the PCF8523 are auto-incrementing after each read or write data byte up to register 13h. After register 13h, the auto-incrementing will wrap around to address 00h (see Fig 6. Table 4. Registers overview Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. ...
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... NXP Semiconductors Table 4. Registers overview Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Address Register name CLOCKOUT and timer registers 0Fh Tmr_CLKOUT_ctrl 10h Tmr_A_freq_ctrl 11h Tmr_A_reg 12h Tmr_B_freq_ctrl 13h Tmr_B_reg PCF8523 Product data sheet … ...
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... NXP Semiconductors 8.2 Control and status registers 8.2.1 Register Control_1 Table 5. Bit [1] Default value. [2] Must always be written with logic 0. [3] For a software reset, 01011000 (58h) must be sent to register Control_1 (see always return 0 when read. PCF8523 Product data sheet Control_1 - control and status register 1 (address 00h) bit description ...
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... NXP Semiconductors 8.2.2 Register Control_2 Table 6. Bit [1] Default value. PCF8523 Product data sheet Control_2 - control and status register 2 (address 01h) bit description Symbol Value [1] WTAF 0 1 [1] CTAF 0 1 [1] CTBF [1] WTAIE 0 1 [1] CTAIE 0 1 [1] ...
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... NXP Semiconductors 8.2.3 Register Control_3 Table 7. Bit [1] Default value is 111. [2] Default value. PCF8523 Product data sheet Control_3 - control and status register 3 (address 02h) bit description Symbol Value PM[2:0] see Table [2] BSF 0 1 [2] BLF 0 1 [2] BSIE 0 1 [2] BLIE 0 1 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 8.3 Reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. Software reset command means setting bits 6, 4, and 3 in register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see ...
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... NXP Semiconductors After reset, the following mode is entered: • 32.768 kHz CLKOUT active • 24 hour mode is selected • Register Offset is set logic 0 • No alarms set • Timers disabled • No interrupts enabled • Battery switch-over is disabled • Battery low detection is disabled • ...
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... NXP Semiconductors SIE SECONDS COUNTER from interface: clear SF COUNTDOWN COUNTER A TAC = 01 ENABLE from interface: clear CTAF WATCHDOG COUNTER A TAC = 10 ENABLE MCU loading watchdog counter or reading WTAF COUNTDOWN COUNTER B TBC = 1 ENABLE from interface: clear CTBF set alarm flag, AF from interface: clear AF offset circuit: ...
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... NXP Semiconductors 8.5 Power management functions The PCF8523 has two power supply pins: • • V BAT The PCF8523 has two power management functions implemented: • Battery switch-over function, • Battery low detection function. The power management functions are controlled by the control bits PM[2:0] in register Control_3 (02h): Table 9 ...
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... NXP Semiconductors 8.5.2 Battery switch-over function The PCF8523 has a backup battery switch-over circuit, which monitors the main power supply V condition is detected. One of two operation modes can be selected: • Standard mode: the power failure condition happens when • Direct switching mode: the power failure condition happens when V ...
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... NXP Semiconductors 8.5.2.1 Standard mode If V > < th(sw)bat (= 2 BSF INT1 Fig 9. PCF8523 Product data sheet OR V > V the internal power supply is V BAT DD th(sw)bat AND V < V the internal power supply is V BAT DD th(sw)bat backup battery operation ...
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... NXP Semiconductors 8.5.2.2 Direct switching mode If V > < The direct switching mode is useful in systems where V (e. and V BAT power consumption is reduced compared to the standard mode because the monitoring of V and th(sw)bat (= 2 BSF INT1 Fig 10. Battery switch-over behavior in direct switching mode and with bit BSIE set 8 ...
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... NXP Semiconductors An unreliable battery will not ensure data integrity during periods of backup battery operation. When V Figure 11): 1. The battery low flag BLF is set logic interrupt is generated if the control bit BLIE (register Control_3) is enabled. The interrupt remains active until the battery is replaced (BLF set logic 0) or when bit BLIE is disabled (BLIE set logic 0) ...
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... NXP Semiconductors 8.6 Time and date registers Most of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the array SECONDS in Table 11. 8.6.1 Register Seconds Table 10. Bit [1] Start-up value. Table 11. ...
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... NXP Semiconductors V oscillation OS flag Fig 12. OS flag 8.6.2 Register Minutes Table 12. Bit 8.6.3 Register Hours Table 13. Bit hour mode hour mode [1] Hour mode is set by bit 12_24 in register Control_1 (see 8.6.4 Register Days Table 14. ...
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... NXP Semiconductors 8.6.5 Register Weekdays Table 15. Bit Table 16. [1] Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday [1] Definition may be re-assigned by the user. 8.6.6 Register Months Table 17. Bit Table 18. Month January February March April May June July August ...
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... NXP Semiconductors 8.6.7 Register Years Table 19. Bit 8.6.8 Data flow of the time function Figure 13 Fig 13. Data flow diagram of the time function During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents: • Faulty reading of the clock and calendar during a carry condition, • ...
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... NXP Semiconductors Because of this method very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted example, if the time (seconds through to hours) is set in one access and then in a second access the date is set possible that the time will increment between the two accesses ...
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... NXP Semiconductors 8.7.3 Register Day_alarm Table 22. Bit [1] Default value. 8.7.4 Register Weekday_alarm Table 23. Bit [1] Default value. 8.7.5 Alarm flag (1) Only when all enabled alarm settings are matching. Fig 15. Alarm function block diagram PCF8523 Product data sheet ...
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... NXP Semiconductors When one or several alarm registers are loaded with a valid minute, hour, day, or weekday value and its corresponding alarm enable bit (AE_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday value. When all enabled comparisons first match, the alarm flag, AF (register Control_2), is set logic 1. ...
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... NXP Semiconductors 8.7.6 Alarm interrupts Generation of interrupts from the alarm function is controlled via the bit AIE (register Control_1). If AIE is enabled, the INT1 will follow the status of bit AF (register Control_2). Clearing AF will immediately clear INT1. No pulse generation is possible for alarm interrupts. Fig 17. AF timing ...
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... NXP Semiconductors 8.8 Register Offset The PCF8523 incorporates an offset register (address 0Eh), which can be used to implement several functions, like: • Aging adjustment, • Temperature compensation, • Accuracy tuning. Table 26. Bit [1] Default value. Each LSB will introduce an offset of 4.34 ppm for MODE = 0 and 4.069 ppm for MODE = 1. The values of 4.34 ppm and 4.069 ppm are based on a nominal 32.768 kHz clock. The offset value is coded in two’ ...
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... NXP Semiconductors 8.8.1 Correction when MODE = 0 The correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values have been implemented. Table 28. Correction value +1 or − − −3 : +59 or −59 +60 or −60 +61 or − ...
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... NXP Semiconductors Table 30. Correction value +1 or − − −3 : +59 or −59 +60 or −60 +61 or −61 +62 or −62 +63 or −63 −64 [1] The correction pulses on pin INT1 are ⁄ 1 2048 In MODE = 1, any timer source clock using a frequency below 4.096 kHz will be also affected by the clock correction (see Table 31 ...
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... NXP Semiconductors 8.9 Timer function The PCF8523 has three timers: • Timer A can be used as a watchdog timer or a countdown timer (see can be configured by using TAC[1:0] in the Tmr_CLKOUT_ctrl register (0Fh). • Timer B can be used as a countdown timer (see by using TBC in the Tmr_CLKOUT_ctrl register (0Fh). ...
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... NXP Semiconductors A programmable square wave is available at pin INT1/CLKOUT and pin CLKOUT, which are both open-drain outputs. Pin INT1/CLKOUT has both functions of INT1 and CLKOUT combined. The duty cycle of the selected clock is not controlled but due to the nature of the clock generation, all clock frequencies except 32.768 kHz have a duty cycle 50. ...
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... NXP Semiconductors 8.9.1.3 Register Tmr_A_reg Table 35. Bit 8.9.1.4 Register Tmr_B_freq_ctrl Table 36. Bit [1] Default value. 8.9.1.5 Register Tmr_B_reg Table 37. Bit PCF8523 Product data sheet Tmr_A_reg - timer A value register (address 11h) bit description Symbol Value TIMER_A_VALUE[7: Tmr_B_freq_ctrl - timer B frequency control register (address 12h) bit ...
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... NXP Semiconductors 8.9.1.6 Programmable timer characteristics Table 38. TAQ[2:0] TBQ[2:0] 000 001 010 011 111 110 100 8.9.2 Timer A With the bit field TAC[1:0] in register Tmr_CLKOUT_ctrl (0Fh) Timer A can be configured as a countdown timer (TAC[1:0] = 01) or watchdog timer (TAC[1:0] = 10). 8.9.2.1 Watchdog timer function The three bits TAQ[2:0] in register Tmr_A_freq_ctrl (10h) determine one of the five source clock frequencies for the watchdog timer: 4 ...
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... NXP Semiconductors • The watchdog timer stops. WTAF is read only. A read of the register Control_2 (01h) will automatically reset WTAF (WTAF = 0) and clear the interrupt. watchdog timer value WTAF Fig 18. Watchdog activates an interrupt when timed out 8.9.2.2 Countdown timer function When configured as a countdown timer (TAC[1:0] = 01), timer A counts down from the software programmed 8-bit binary value n in register Tmr_A_reg (11h) ...
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... NXP Semiconductors countdown value, n timer source clock countdown counter Fig 19. General countdown timer behavior At the end of every countdown, the timer sets the countdown timer flag CTAF (register Control_2). CTAF may only be cleared by using the interface. Instructions, how to clear a flag, is given in When reading the timer, the current countdown value is returned and not the initial value n ...
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... NXP Semiconductors When the interrupt generation is enabled (CTAIE = 1) and the countdown timer flag CTAF is set logic 1, an interrupt signal on INT1 will be generated. The interrupt may be generated as a pulsed signal every countdown period permanently active signal, which follows the condition of CTAF (register Control_2). The TAM bit (register Tmr_CLKOUT_ctrl) is used to control this mode selection ...
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... NXP Semiconductors If a new value written before the end of the actual timer-period, this value will take immediate effect not recommended to change n without first disabling the counter by setting TBC logic 0 (register Tmr_CLKOUT_ctrl). The update asynchronous to the timer clock. Therefore changing it on the fly could result in a corrupted value loaded into the countdown counter ...
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... NXP Semiconductors INT1 when SIE enabled Fig 21. Example for second interrupt when TAM = 1 Fig 22. Example for second interrupt when TAM = 0 8.9.5 Timer interrupt pulse The timer interrupt is generated as a pulsed signal when TAM or TBM are set logic 1. The pulse generator for the timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the timer and on the timer register value n. Consequently, the width of the interrupt pulse varies ...
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... NXP Semiconductors Table 42. Pulse mode, bit TBM set logic 1. Source clock (Hz). 4096 64 1 ⁄ ⁄ 1 3600 [ loaded timer register value. Timer stops when [2] If pulse period is shorter than the setting via bit TBW, the interrupt pulse width is set to 15.625 ms. ...
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... NXP Semiconductors (1) Indicates normal duration of INT1 pulse. Fig 24. Example of shortening the INT1 pulse by clearing the CTAF flag PCF8523 Product data sheet countdown counter 01 n CDTF INT1 SCL instruction The timing shown for clearing CTAF is also valid for the non-pulsed interrupt mode, i.e. when TAM set logic 0, where the INT1 pulse may be shortened by setting CTAIE logic 0 ...
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... NXP Semiconductors 8.10 STOP bit function The STOP bit function allows the accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler ( ticks will be generated. The time circuits can then be set and will not increment until the STOP bit is released (see Fig 25 ...
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... NXP Semiconductors Table 43. First increment of time circuits after stop release [1] Bit Prescaler bits STOP Clock is running normally 0 01-0000111010100 STOP is activated by user XX-0000000000000 New time is set by user 1 XX-0000000000000 STOP is released by user 0 XX-0000000000000 0 XX-1000000000000 0 XX-0100000000000 0 XX-1100000000000 : : 0 11-1111111111110 ...
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... NXP Semiconductors 2 8.11 I C-bus interface 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER RECEIVER Fig 29. System configuration The PCF8523 can act as a slave transmitter and a slave receiver. 8.11.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • ...
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... NXP Semiconductors 2 8.11.5 I C-bus protocol 2 One I C-bus slave address (1101000) is reserved for the PCF8523. The entire I slave address byte is shown in Table 44. Bit After a start condition, a valid hardware address has to be sent to a PCF8523 device. The R/W bit defines the direction of the following single or multiple byte data transfer. For ...
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... NXP Semiconductors 9. Internal circuitry Fig 33. Device diode protection diagram of PCF8523 PCF8523 Product data sheet PCF8523 OSCI OSCO V BAT V SS INT2 All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 January 2011 PCF8523 Real-Time Clock (RTC) and calendar V DD INT1/CLKOUT SCL ...
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... NXP Semiconductors 10. Limiting values Table 45. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol BAT P tot V ESD stg T amb [1] Pass level; Human Body Model (HBM), according to [2] Pass level; Charged-Device Model (CDM), according to [3] Pass level ...
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... NXP Semiconductors 11. Static characteristics Table 46. Static characteristics specified. Symbol Parameter Supplies V supply voltage DD SR slew rate V battery supply voltage BAT I supply current DD I battery leakage current L(bat) Power management V battery switch threshold th(sw)bat voltage Inputs V LOW-level input voltage ...
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... NXP Semiconductors Table 46. Static characteristics specified. Symbol Parameter I LOW-level output OL current I output leakage current LO C integrated load L(itg) capacitance R series resistance S [1] For reliable oscillator start at power-up: V ⁄ 1 [2] Timer source clock = Hz, level of pins SCL and SDA is V ...
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... NXP Semiconductors 12. Dynamic characteristics 2 Table 47. I C-bus interface timing All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference and 70 % with an input voltage swing of V Symbol Parameter Pin SCL f SCL clock frequency SCL t LOW period of the SCL clock - ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA 2 Fig 34. I C-bus timing diagram; rise and fall times refer and 70 % 13. Application information OSCI OSCO V BAT R and C are recommended to limit the Slew Rate (SR, see 1 1 the battery is not guaranteed. ...
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... NXP Semiconductors 14. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0 0.2 0.00 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Bare die outline Bare die; 12 bumps (6- European projection Fig 39. Bare die outline of PCF8523U (for dimensions see Table 48. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension includes saw lane. [2] P and P 1 [3] P and P 2 PCF8523 ...
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... NXP Semiconductors Table 49. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol V DD OSCI OSCO V BAT V SS n.c. INT2 CLKOUT SDA SCL n.c. INT1/CLKOUT Table 50. Coordinates Location Dimension [1] The x/y coordinates of the alignment mark location represent the position of the REF point (see with respect to the center (x the chip ...
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... NXP Semiconductors 17. Packing information 1.492 mm 1 1.449 straight edge of the wafer (1) Die marking code. Seal ring plus gap to active circuit ~18 μm. Wafer thickness 200 μm. PCF8523U: bad die are marked in wafer mapping. Fig 41. PCF8523U wafer information plastic frame ∅ 250 mm 276 mm Fig 42 ...
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... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 43. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8523 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 19. Abbreviations Table 53. Acronym AM BCD CDM CMOS DC FFC HBM LSB MCU MSB MSL PCB PM POR PPM RTC SCL SDA SMD SR PCF8523 Product data sheet Abbreviations Description Ante Meridiem Binary Coded Decimal Charged-Device Model Complementary Metal Oxide Semiconductor Direct Current ...
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... NXP Semiconductors 20. References [1] AN10365 — Surface mount reflow soldering description [2] AN10706 — Handling bare die [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for ...
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... NXP Semiconductors 21. Revision history Table 54. Revision history Document ID Release date PCF8523 v.2 20110127 • Modifications: Adjusted test criteria in • Enhanced specification of battery switch threshold voltage in PCF8523 v.1 20101123 PCF8523 Product data sheet Data sheet status Product data sheet Table 46 Product data sheet All information provided in this document is subject to legal disclaimers. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Register overview . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Control and status registers . . . . . . . . . . . . . . . 9 8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10 8.2.3 Register Control_3 . . . . . . . . . . . . . . . . . . . . . 11 8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 ...