m48t512y STMicroelectronics, m48t512y Datasheet - Page 8
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m48t512y
Manufacturer Part Number
m48t512y
Description
5.0 Or 3.3v, 4 Mbit 512 Kbit X 8 Timekeeper Sram
Manufacturer
STMicroelectronics
Datasheet
1.M48T512Y.pdf
(21 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
m48t512y-70PM1
Manufacturer:
NIPPON
Quantity:
34 000
M48T512Y, M48T512V*
WRITE Mode
The M48T512Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of t
Figure 6. WRITE AC Waveforms, WRITE Enable Controlled
Figure 7. WRITE AC Waveforms, Chip Enable Controlled
8/21
A0-A18
E
W
DQ0-DQ7
A0-A18
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVEL
tAVWL
EHAX
tWLQZ
from
tAVEH
tAVWH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs t
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
WLQZ
tEHDX
from WRITE Enable prior to
DVWH
tWHQX
after W falls.
tEHAX
tWHAX
prior to the end of
WHDX
AI02386
AI02387
afterward. G