max5893egk-d Maxim Integrated Products, Inc., max5893egk-d Datasheet - Page 16

• Manufacturer Part Number: max5893egk-d
• Description: Max5893 12-bit, 500msps Interpolating And Modulating Dual Dac With Cmos Inputs
• Manufacturer: Maxim Integrated Products, Inc.

12-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Address 00h
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Note: If both bit 2 and bit 3 are 1, the MAX5893 is in
full-power-down mode, leaving only the serial interface
active.
Address 01h
Bits 7, 6 Configure the interpolation filters according
Bit 5
Bits 4, 3 Configure the modulation frequency accord-
Bit 2
Bit 1
16
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Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port will use LSB first
address/data format.
When set to a logic 1, all registers reset to
their default state (this bit included).
Logic 1 stops the clock to the digital interpo-
lators. DAC outputs hold last value prior to
interpolator power-down.
IDAC power-down mode. A logic 1 to this bit
powers down the IDAC.
QDAC power-down mode. A logic 1 to this bit
powers down the QDAC.
Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
able for f
Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e
when used with an external quadrature mod-
to the following table:
00
01
10
11
Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
ing to the following table:
00
01
10
11
where f
modulator.
-jw
(default), cancelling the upper image
1x (no interpolation)
2x
4x
8x (default)
No modulation
f
f
f
IM
IM
IM
IM
IM
/ 2 modulation
/ 4 modulation (default)
/ 4 modulation
is the data rate at the input of the
/ 4 modulation.
Address 02h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Address 03h
Bits 7–0 Unused.
Address 04h
Bits 7–0 These 8 bits define the binary number for
Address 05h
Bits 3–0 These four bits define the binary number for
Address 06h, Bits 7 to 0; Address 07h, Bit 1 and Bit 0
ulator. A logic 1 sets the complex modulation
to be e
used with an external quadrature modulator.
Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Logic 0 (default) configures the data bus for
single-port, interleaved I/Q data. I and Q data
enter through one 12-bit bus. Logic 1 config-
ures the data bus for dual-port I/Q data. I and
Q data enter on separate buses.
Logic 0 (default) configures the data clock
for pin 14. A logic 1 configures the data clock
for pin 27 (DATACLK/B10).
Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Logic 0 (default) configures the DATACLK
pin (pin 14 or pin 27) to be an input. A logic 1
configures the DATACLK pin to be an output.
Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
the coarse-gain adjustment of the IDAC full-
scale current (see the Gain Adjustment sec-
tion). Bit 3 is the MSB. Default is all ones.
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
+jw
, cancelling the lower image when