stlc3040 STMicroelectronics, stlc3040 Datasheet - Page 14

• Manufacturer Part Number: stlc3040
• Description: Subscriber Line Interface Codec Filter, Cofislic
• Manufacturer: STMicroelectronics

STLC3040
message is transferred, E bit and A bit are forced
to inactive state (high = 5V).
A transmission is started by the sender (Transmit
section of the Monitor channel protocol handler)
by putting the E bit from inactive to active state
(low = 0V) and by sending the first byte on Moni-
tor channel in the same frame. Transmission of a
message is allowed only if A bit, sent from the re-
ceiver, has been set inactive for at least one con-
secutive frame. When the receiver is ready, it vali-
dates the incoming byte when received identical
in two consecutive frames. Then, the receiver
sets A bit from the inactive to the active state
(preacknowledgement) and maintain active at
least in the following frame (acknowledgement).
If validation is not possible (two last bytes re-
ceived are not identical) the receiver aborts the
message by setting the A bit active for only a sin-
gle frame.The second byte can be transmitted by
the sender putting the E bit from the active to the
inactive state and sending the second byte on the
Monitor channel in the same frame . The E bit is
set inactive for only one frame. If it remains inac-
tive more than one frame, it means an end of
message. The second byte may be transmitted
only after receiving of the pre-acknowledgement
of the previous byte . Each byte has to be trans-
mitted at least in two consecutive frames.
The receiver validates the current received byte
as for the first one and then set the A bit in the
next two frames first from the active state to the
inactive state (pre-acknowledgement) and back to
the active (acknowledgement). If the receiver can-
not validate the received current byte (two bytes
received not identical)it pre-acknowledges nor-
mally but lets the A bit in the inactive state in the
next frame which indicates an abort request . If a
message sent by the COFISLIC is aborted, the
COFISLIC will send again the complete message
until receiving of an acknowledgement . A mes-
sage received by the COFISLIC can be acknow-
ledged or aborted with flow Control.
The most significant bit (MSB) of Monitor byte is
sent first on the Monitor channel. E & A bits are
active low and inactive state on DU is 5 V. When
no byte is transmitted, Monitor channel time slot
on DU is in the high impedance state.
The GCI interface transmitter will abort after 8
times during which it hasn’t succesfully received
any acknowledge from the device upstream. The
GCI interface receiver will go in abort request
mode after 8 times of unsuccessful attempts to
get 2 identical copies of the data. This means that
after 8 frames of unsuccessful handshake, the
GCI interface transmitter will abort while the re-
ceiver will make a request for abort.
4.6.1 B1/B2 Channels
4.6.1.1 PCM codifications
GCI interface extracts receiving PCM data from
14/49
the B1 channel on DD pin and outputs PCM bytes
on DU pin.
4.6.1.2 Linear codification
STLC3040 allows Linear codification simply set-
ting two bits of CR12 register.
COMTX (bit 0) enables the linear code in trans-
mission, while COMRX (bit 1) enables the linear
code in receive.
STLC3040’s linear code consists of 16 bits which
means a range from (-2
is housed in B1 and B2 channels, B1 is the least
significant byte end B2 is the most significant
byte.
15 bits are dedicated to the module while the
most significant bit is the sign bit.
If bit 15 (sign bit) = 0 bit 14.....bit 0 represent the
module.
If bit 15 = 1 module is got by 2-complementing bit
14 ...... bit 0.
4.6.2 C/I Channel
Command/Indicate byte is a 6 bits wide command
full duplex transmission.
Internal C/I registers will be loaded if downstream
command is stable for two frames.
Also upstream Command/Indicate byte lasts for at
least two consecutive 8KHz frames. Com-
mand/Indicate is mainly used to set SLIC operat-
ing mode and to monitor subscriber On/Off-Hook
and Ground-Key detection.
Any change of line conditions like On-Off/Hook
and Ground Key is signalled via upstream C/I.
HOOK and GNDK bits always reflect line condi-
tions even if corresponding bits of Signalling Reg-
ister are masked by CR12 register. Bit 5 of up-
stream Command/Indicate says that at least one
of Signalling Register six most significant bits has
changed its logical value.
Bit 5 of upstream Command/Indicate does not
change if related bits of Signalling Register have
been masked by CR12 register.
Input/Output pins (IO1/2,I1,O1) can be set and
monitored by C/I channel too. Note that there is
no address in both directions because there is
one GCI time slot per each COFISLIC.
C/I channel in Downstream direction consists of
six bits as shown below :
Basically the first 3 Most significant Bits of C/I
downstrean operate as follows. For a complete
description please refer to Table 13.
RING
BIT7
CONV
BIT6
BIT5
TIM
15
) to (2
BIT4
IO1
15
-1) Linear Code
BIT3
IO2
BIT2
O1