stlc1511 STMicroelectronics, stlc1511 Datasheet - Page 12

• Manufacturer Part Number: stlc1511
• Description: Northenlite?? G.lite Bicmos Analog Front-end Circuit
• Manufacturer: STMicroelectronics

STLC1511
3.4 Phase Lock Loop
The STLC1511 has been intended for use in either
the Central Office application (CO) using an external
clock of 35.328MHz, in the Central Office application
using an external 2.56Mhz clock and on-ship PLL , or
in a Customer Premise Equipment application (CPE).
In the CO application (External Clock Mode), the ref-
erence clock used for the converters and internally in
the STLC1511 is provided by an external reference.
In the CO application (Oscillator Mode), the
STLC1511 provides the ability to drive a LC oscillator
and generate the require clocks using an on-chip
Table 4. PLL Application Modes
3.4.1 Central Office (External Clock Mode)
In CO External Clock Mode the 35.328MHz refer-
ence clock on pin FREF is divided down and used in
both the TX and RX converters. In this mode of oper-
ation, the PLL and oscillator driver are powered
down.
External Clock Mode is selected by setting b5:b0 of
register “AFE Control 4” to “000000”. See section 3.7
for more information.
3.4.2 Central Office (Oscillator Mode)
In Oscillator Mode the 2.56MHz reference clock on
pin FREF is used as the reference clock for the
STLC1511 PLL. This clock is used to lock the LC os-
cillator frequency to 88.32MHz which is further divid-
ed down to provide the sampling clocks to both the
TX and RX converters and passed to the digital ASIC
STLC1510 as its PLL reference on the pin DIGREF.
The clock supplied to the digital ASIC STLC1510 via
12/31
CO External Clock Mode
CO Oscillator Mode
CPE Mode
PLL Misc. 1
PLL Misc. 2
PLL Misc. 3
<1>Presently only applications described in this table are supported.
<2>The clock jitter specification for an externally supplied DAC or ADC clock (on pins FREF when in CO External Clock mode) is the
same as the jitter specification for the PLL.
Description
2
2.56
35.328
N/A
1.536
2.048
4.096
FREF
1
MHz
freq
35.328
17.664
35.328
35.328
35.328
35.328
DIGREF
MHz
freq
In the CPE application the tuning signal must be pro-
vided by the digital modem ASIC (STLC1510).
DIGREF is running at a rate of 17.664MHz in this
mode.
connected as shown in Figure 3, "CO Frequency vs.
Tuning Voltage".
CO Oscillator mode is selected by setting b5:b0 in
register “AFE Control 5” to “001001”. See section
"Digital Interface And Memory Map" on page 20 for
more information.
PLL. In the Customer Premise Equipment (CPE) ap-
plication, the STLC1511 provides the crystal driver
for use with a external crystal and feedback network.
While the above descriptions highlight the intended
applications, the STLC1511 also has the flexibility to
provide a PLL function when used with a different ref-
erence frequency and external 35.328MHz crystal.
Table 4 highlights the different PLL modes for the
STLC1511.
No
Yes
No
Yes
Yes
Yes
details the CO PLL and oscillator performance when
active?
PLL
N/A
88.32
N/A
N/A
N/A
N/A
LC Osc
MHz
freq
N/A
35.328
35.328
35.328
N/A
35.328
XTAL
MHz
freq
000000
001001
000110
011110
101110
111110
AFE Control 5
[b5:b0]