stlc1511 STMicroelectronics, stlc1511 Datasheet - Page 26

• Manufacturer Part Number: stlc1511
• Description: Northenlite?? G.lite Bicmos Analog Front-end Circuit
• Manufacturer: STMicroelectronics

STLC1511
3.8 TIMING
Table 17. describes the timing relationships between important signals.
Table 17. Timing
3.9 POWER UP RESET
When the voltage on the RESETN pin is low the bits in the control register will be reset as per the detailed reg-
ister maps in “Digital Interface And Memory Map” on page 20.
In addition, digital output pins, DTX, FRMCLK, and RXSOUT[1:0] are high impedance. The other digital outputs
are always as defined in Table 1 on page 2.
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t
t
t
t
t
t
t
t
t
t
t
t
Symbol
SENB
HENB
SDRX
HDRX
DDTX
SCK35
HCK35
DRX
DFC
DDRCK35
RDIGREF
FDIGREF
<1>Load on all output pads assumed to be < 25pF.This gives a delay through the TLCHT pad of approximately 5ns.
ENB falling to DIGCLK rising
ENB rising to DIGCLK falling
Data in valid to DIGCLK falling
DIGCLK falling to Data in hold
DIGCLK rising to Data out valid
TXSIN[1:0] valid to CK35M falling
CK35M falling to TXSIN[1:0] hold
CK35M rising to RXSOUT[1:0] valid
CK35M rising to FRMCLK valid
DIGREF rising to CK35M rising
DIGREF rise time (20% to 80%)
DIGREF fall time (80% to 20%)
Parameter
2
1
1
2
2
2
10
1
1
Spec
Min
5
5
5
5
5
5
5
5
5
12
2
2
Typ
1
10
10
10
20
3
3
Spec
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
s