adc12010civyx National Semiconductor Corporation, adc12010civyx Datasheet - Page 16

• Manufacturer Part Number: adc12010civyx
• Description: 12-bit, 10 Msps, 160 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
Operating on a single +5V supply, the ADC12010 uses a
pipeline architecture with error correction circuitry to help
ensure maximum performance. The differential analog input
signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving
that pin.
The output word rate is the same as the clock frequency,
which can be between 100 kSPS and 15 MSPS (typical).
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by
the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 40 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12010:
1.1 Analog Inputs
The ADC12010 has two analog signal inputs, V
These two pins form a differential input pair. There is one
reference input pin, V
1.2 Reference Pins
The ADC12010 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of
1.0V to 2.4V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12010. Increasing the
reference voltage (and the input signal swing) beyond 2.4V
will degrade THD for a full-scale input. It is very important
that all grounds associated with the reference voltage and
the input signal make connection to the analog ground plane
at a single point to minimize the effects of noise currents in
the ground path.
The three Reference Bypass Pins (V
made available for bypass purposes. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
main between ground and 4V.
The Peaks of the individual input signals (V
should each never exceed the voltage described as
to maintain THD and SINAD performance.
4.75V ≤ V
V
2.35V ≤ V
100 kHz ≤ f
1.0V ≤ V
D
= V
A
REF
A
DR
CLK
≤ 5.25V
≤ 2.4V
≤ V
V
≤ 15 MHz
IN
D
V
+, V
IN
REF
IN
= (V
+ and V
IN
.
− = V
A
IN
/2. The input signals should re-
+) – (V
REF
IN
−. The input signal, V
+ V
IN
RP
−)
, V
CM
RM
IN
and V
IN
+ and V
+ and V
RN
) are
IN
IN
IN
, is
−)
−.
16
The ADC12010 performs best with a differential input with
each input centered around V
swing at both V
value of the reference voltage or the output data will be
clipped. The two input signals should be exactly 180˚ out of
phase from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For a complex waveform, however,
angular errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
Where dev is the angular difference, in degrees, between
the two signals having a 180˚ relative phase relationship to
each other (see Figure 3). Drive the analog inputs with a
source impedance less than 100Ω.
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, V
voltage, V
V
V
V
V
FIGURE 3. Angular Errors Between the Two Input
CM
CM
CM
CM
TABLE 1. Input to Output Relationship —
V
− V
V
− V
+ V
+ V
FIGURE 2. Expected Input Signal Range
IN
CM
Signals Will Reduce the Output Level
CM
REF
+
REF
REF
REF
REF
.
, and be centered around a common mode
/4
/4
/2
/2
IN
+ and V
Differential Input
V
V
V
V
E
CM
CM
CM
CM
FS
IN
= dev
V
V
+ V
+ V
− V
− V
− each should not exceed the
IN
CM
CM
−
REF
REF
REF
REF
. The peak-to-peak voltage
1.79
/2
/4
/4
/2
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0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
Output