adc12010civyx National Semiconductor Corporation, adc12010civyx Datasheet - Page 21

• Manufacturer Part Number: adc12010civyx
• Description: 12-bit, 10 Msps, 160 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input pins and ground or to the refer-
ence input pin and ground should be connected to a very
clean point in the analog ground plane.
Figure 7 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog ground plane. All digital
circuitry and I/O lines should be placed in the digital area of
the board. Furthermore, all components in the reference
circuitry and the input signal chain that are connected to
ground should be connected together with short traces and
enter the ground plane at a single point. All ground connec-
tions should have a low inductance path to ground.
We do not recommend a split ground plane. Rather, using
wide power traces with analog and digital power traces
well-separated from each other, and keeping analog and
digital signal lines well-separated from each other will mini-
mize noise while keeping EMI to tolerable levels.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
(Continued)
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pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12010 with
a device that is powered from supplies outside the range of
the ADC12010 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 25 pF/pin
will cause t
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12010, which reduces the energy coupled back into the
converter output pins by limiting the output current. A rea-
sonable value for these resistors is 47Ω to 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor and shunt capacitor at each
amplifier output (as shown in Figure 5) will improve perfor-
mance. The LMH6702 and the LMH6628 have been suc-
cessfully used to drive the analog inputs of the ADC12010.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting con-
figuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the speci-
fied range. As mentioned in Section 1.2, V
the range of
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
OD
to increase, making it difficult to properly latch
DR
and DR GND. These large charging cur-
1.0V ≤ V
REF
≤ 2.4V
REF
o
should be in
out of phase
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