adc12010civyx National Semiconductor Corporation, adc12010civyx Datasheet - Page 7

• Manufacturer Part Number: adc12010civyx
• Description: 12-bit, 10 Msps, 160 Mw A/d Converter With Internal Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Symbol
f
f
t
t
t
t
t
t
t
t
t
CLK 1
CLK 2
CH
CL
CONV
OD
AD
AJ
DIS
EN
PD
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 180 mW (160 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤4.85V to ensure accurate conversions.
Note 8: To guarantee accuracy, it is required that |V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for this application.
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
+3.0V, PD = 0V, V
T
MAX
: all other limits T
JA
is 79˚C/W, so P
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
Data Output Delay after Rising
CLK Edge
Aperture Delay
Aperture Jitter
Data outputs into TRI-STATE
Mode
Data Outputs Active after
TRI-STATE
Power Down Mode Exit Cycle
REF
D
MAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
Parameter
A
= +2.0V, f
= T
A
= T
J
REF
J
= 25˚C (Notes 7, 8, 9, 12)
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
JA
= +2.0V (4V
CLK
), and the ambient temperature, (T
= 10 MHz, t
A
P-P
–V
D
differential input), the 12-bit LSB is 977 µV.
J
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
V
V
0.1 µF cap on pins 30, 31,32
r
IL
DR
DR
= t
= 0.4V for a falling edge and V
f
= 2.5V
= 3.0V
= 3 ns, C
A
), and can be calculated using the formula P
Conditions
7
IN
A
L
or below GND by more than 100 mV. As an example, if V
= 25 pF/pin. Boldface limits apply for T
<
AGND, or V
A
or below GND will not damage this device, provided current is limited per
20051607
IH
IN
= 2.4V for a rising edge.
>
V
A
), the current at that pin should be limited to 25 mA. The
(Note 10)
Typical
100
500
1.2
10
11
11
2
4
4
D
MAX = (T
A
(Note 10)
= V
J
Limits
max - T
16.8
16.8
15
30
30
D
A
6
A
= +5V, V
= T
is 4.75V, the full-scale
A
)/θ
J
= T
JA
www.national.com
. In the 32-pin
MHz (min)
ns (max)
ns (max)
MIN
ns (min)
DR
(Limits)
ns(min)
Cycles
ps rms
Units
Clock
J
kHz
max, the
ns
ns
ns
ns
=
to