tda8007bhl/c3 NXP Semiconductors, tda8007bhl/c3 Datasheet - Page 14

• Manufacturer Part Number: tda8007bhl/c3
• Description: Double Multiprotocol Ic Card Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4 Description of HSR bits.
When at least one of the bits PRTL2, PRTL1, PRL2, PRL1
or PTL is HIGH, then INT is LOW. The bits having caused
the interrupt are cleared when register HSR has been
read-out. The same occurs with INTAUXL, if not disabled.
In case of an emergency deactivation (by bits PRTL2,
PRTL1, SUPL, PRL2, PRL1 or PTL), bit START (bit 0 in
the PCR) is automatically reset by hardware.
At power-on, or after a supply voltage drop-out, bit SUPL
is set and pin INT = LOW. Pin INT will return to HIGH level
at the end of the alarm pulse RSTOUT (see Fig.13).
Bit SUPL will be reset only after a status register read-out
outside the alarm pulse.
Table 5 Register TOR1 (address 09H; write only); note 1
Note
1. Register value at reset: all bits are cleared after reset.
Table 6 Register TOR2 (address 0AH; write only); note 1
Note
1. Register value at reset: all bits are cleared after reset.
Table 7 Register TOR3 (address 0BH; write only); note 1
Note
1. Register value at reset: all bits are cleared after reset.
2003 Feb 18
BIT
Double multiprotocol IC card interface
7
6
5
4
3
2
1
0
TOL15
TOL23
TOL7
7
7
7
SYMBOL
INTAUXL Auxiliary interrupt change. Bit INTAUXL = 1 if the level on pin INTAUX has been changed.
PRTL2
PRTL1
SUPL
PRL2
PRL1
HS7
PTL
TOL14
TOL22
not used
Protection 2. Bit PRTL2 = 1 when a fault has been detected on card reader 2. Bit PRTL 2 is the
OR-function of the protection on pin V
Protection 1. Bit PRTL1 = 1 when a fault has been detected on card reader 1. Bit PRTL 1 is the
OR-function of the protection on pin V
Supervisor Latch. Bit SUPL = 1 when the supervisor has been activated.
Presence Latch 2. Bit PRL2 = 1 when a level change has occurred on pin PRES2.
Presence Latch 1. Bit PRL1 = 1 when a level change has occurred on pin PRES1.
Overheating. Bit PTL = 1 if overheating has occurred.
TOL6
6
6
6
TOL13
TOL21
TOL5
5
5
5
TOL12
TOL20
TOL4
4
4
4
CC2
CC1
14
DESCRIPTION
A minimum time of 2 s is needed between two
successive read operations of register HSR, as well as
between reading of register HSR and activation (write in
register PCR).
8.2.1.3
The three Time-Out Registers (TOR1, TOR2 and TOR3)
form a programmable 24-bit ETU counter, or two
independant counters (one 16-bit and one 8-bit). The
value to load in registers TOR1, TOR2 and TOR3 is the
number of ETU to count. The time-out counters may only
be used when a card is active with a running clock.
and pin RST2.
and pin RST1.
TOL11
TOL19
TOL3
3
3
3
Time-out registers
TOL10
TOL18
TOL2
2
2
2
TOL17
TOL1
TOL9
1
1
1
Product specification
TDA8007B
TOL16
TOL0
TOL8
0
0
0