tda8020hl-c2 NXP Semiconductors, tda8020hl-c2 Datasheet - Page 8

• Manufacturer Part Number: tda8020hl-c2
• Description: Dual Smart Card Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
DC-to-DC converter
V
the supply voltage for card 2 contacts. Card 1 and card 2
may be independently powered-down, powered at 5 V or
powered at 3 V. A capacitor type step-up converter is used
for generating these voltages. This step-up converter acts
either as a doubler, tripler or follower. An hysteresis of
100 mV is present on the different threshold voltages.
If V
are 5 possible situations:
The output voltage, V
generators. V
a reference for all other cards contacts.
The sum of I
means that when a card is drawing its maximum current
(around 60 mA at V
other card should be set in low power consumption mode
(less than 20 or 25 mA). Note that during the card Advice
to Receive (ATR) process, the current may be maximum;
so, a card should only be activated if the other card draws
less than 20 or 25 mA. The DC-to-DC converter is supplied
via separate supply pins V
decoupling separate from the other supply pins.
During normal operation or activation, each card is allowed
to draw independently a current of up to 60 mA at
V
voltage from 2.7 V up to 6.5 V provided the sum of
I
If V
60 mA at the same time.
If V
55 mA at the same time.
2003 Nov 06
CC1
CC1
CC
V
converter acts as a doubler with a regulation of
approximately 4.0 V
V
converter acts as a tripler with a regulation of
approximately 5.5 V
V
converter acts as a follower: V
5.8 V > V
DC-to-DC converter acts as a doubler with a regulation
of approximately 5.5 V
V
converter acts as a follower and V
Dual IC card interface
DD
DD
CC
DD
DD
DD
DD
= 5 V or up to 55 mA at V
and I
is the supply voltage for card 1 contacts and V
is the maximum value of V
> 3 V, for 5 V cards, then both cards can draw up to
> 3 V, for 3 V cards, then both cards can draw up to
< 3.4 V and V
< 3.4 V and V
> 3.5 V and V
> 5.9 V and V
CC2
DD
CC1
CC1
does not exceed 80 mA.
> 3.5 V and V
and I
, V
CC2
CC
CC
CC
CC
CC
UP
CC2
= 5 V, 55 mA at V
and CGND1, CGND2 are used as
= 3 V: in this case, the DC-to-DC
= 5 V: in this case, the DC-to-DC
= 3 V: in this case, the DC-to-DC
= 5 V: in this case, the DC-to-DC
, is fed internally to the V
shall not exceed 80 mA, which
DDA
CC
CC
and AGND to allow
= 5 V: in this case, the
CC1
DD
= 3 V, with a supply
is applied on V
DD
and V
is applied on V
CC
CC2
= 3 V), the
, then there
CC
UP
CC2
UP
is
.
8
I
A 400 kHz I
the device and reading the status.
I
The I
different ICs or modules. The serial bus consists of two
bidirectional lines; one for data (SDA), and one for the
clock (SCL).
Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.
The following protocol has been defined:
B
The following bus conditions have been defined:
D
Each data transfer is initiated with a START condition and
terminated with a STOP condition.
Data transfer is unlimited in the read mode. The
information is transmitted in bytes and each receiver
acknowledges with a ninth bit.
The TDA8020HL operates in standard mode (100 kHz
clock rate) and fast mode (400 kHz clock rate) defined in
the I
By definition, a device that sends a signal is called a
transmitter, and the device which receives the signal is
called a receiver. The device which controls the signal is
2
2
C-bus
C-
US CONDITIONS
ATA TRANSFER
Data transfer may be initiated only when the bus is not
busy
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.
Bus not busy: both data and clock lines remain HIGH
Start data transfer: a change in the state of the data line,
from HIGH-to-LOW, while the clock is HIGH, defines the
START condition
Stop data transfer: a change in the state of the data line,
from LOW-to-HIGH, while the clock is HIGH, defines the
STOP condition
Data valid: the state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per data bit.
BUS PROTOCOL
2
2
C-bus specification.
C-bus is for 2-way, 2-line communication between
2
C-bus slave interface is used for configuring
TDA8020HL
Product specification