hi5766 Intersil Corporation, hi5766 Datasheet - Page 11
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hi5766
Manufacturer Part Number
hi5766
Description
10-bit, 60msps A/d Converter
Manufacturer
Intersil Corporation
Datasheet
1.HI5766.pdf
(16 pages)
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Typical Performance Curves
Detailed Description
Theory of Operation
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 24 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal,
and
sampling phase,
capacitors, C
are discharged to analog ground. At the falling edge of
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between C
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
3.30
3.20
3.10
3.00
FIGURE 21. DC BIAS VOLTAGE (V
φ
2
-40
, derived from the master sampling clock. During the
S
-20
. At the same time the holding capacitors, C
φ
1
, the input signal is applied to the sampling
0
TEMPERATURE (
11
20
φ
2
DC
, the two bottom plates of
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
) vs TEMPERATURE
0
S
o
40
0
C)
and C
(Continued)
100
H
FIGURE 23. 2048 POINT FFT PLOT
60
completing
200
φ
1
300
the
H
80
,
φ
1
FREQUENCY (BIN)
400
HI5766
500
differential output for the converter core. During the sampling
phase, the V
C
typical full power input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
600
-100
S
-10
-20
-30
-40
-50
-60
-70
-80
-90
. The relatively small values of these components result in a
0
0
700
V
V
FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD
IN
IN
+
-
100
800
f
f
T
IN
S
IN
A
φ
φ
FIGURE 22. 2048 POINT FFT PLOT
= 60 MSPS
φ
= 10MHz
= 25
1
1
200
pins see only the on-resistance of a switch and
2
900
o
C
300
C
C
S
S
1023
φ
φ
1
1
FREQUENCY (BIN)
400
500
+
-
+
-
C
C
H
H
600
700
φ
φ
1
1
800
f
f
T
S
IN
A
= 60 MSPS
= 1MHz
V
= 25
V
OUT+
OUT-
900
o
C
1023