hi5766 Intersil Corporation, hi5766 Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/3/342/intersil_corporation_sml.jpg)
hi5766
Manufacturer Part Number
hi5766
Description
10-bit, 60msps A/d Converter
Manufacturer
Intersil Corporation
Datasheet
1.HI5766.pdf
(16 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
hi5766KCAZ
Manufacturer:
Intersil
Quantity:
45
Part Number:
hi5766KCB
Manufacturer:
INTERSIL
Quantity:
20 000
Company:
Part Number:
hi5766KCBZ
Manufacturer:
Intersil
Quantity:
52
Company:
Part Number:
hi5766KCBZ
Manufacturer:
Intersil
Quantity:
35
Part Number:
hi5766KCBZ
Manufacturer:
INTERSIL
Quantity:
20 000
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
Data output delay time is the time to where the new data (N)
is valid.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
AJ
AP
H
)
)
)
16
OD
)
HI5766
Data Latency (t
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
LAT
)