adadc85 Analog Devices, Inc., adadc85 Datasheet - Page 6

• Manufacturer Part Number: adadc85
• Description: Fast, Complete 12-bit A/d Converters
• Manufacturer: Analog Devices, Inc.

AD ADC84/AD ADC85
FUNCTIONAL DESCRIPTION
OFFSET ADJUSTMENT
The zero adjust circuit consists of a potentiometer connected
across ±V
to Comparator Input Pin 22 for all ranges. As shown in Figure 6,
the tolerance of this fixed resistor is not critical, and a carbon
composition type is generally adequate. Using a carbon
composition resistor having a –1200 ppm/°C tempco contrib-
utes a worst-case offset tempco of 8 × 244 × 10
= 2.3 ppm/°C of FSR, if the OFFSET ADJ potentiometer is set at
either end of its adjustment range. Since the maximum offset
adjustment required is typically no more than ±4 LSB, use of a
carbon composition offset summing resistor typically
contributes no more than 1 ppm/°C of FSR offset tempco.
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco <100 ppm/°C) are
used, is shown in Figure 7.
In either zero adjust circuit, the fixed resistor connected to Pin
22 should be located close to this pin to keep the pin connection
runs short. (Comparator Input Pin 22 is quite sensitive to
external noise pickup).
GAIN ADJUSTMENT
The gain adjust circuit consists of a potentiometer connected
across ±V
the Gain Adjust pin 27 as shown in Figure 8.
S
S
with its slider connected through a 1.8 MΩ resistor
with its slider connected through a 10MΩ resistor to
Figure 7. Low Tempco Zero Adjustment Circuit
Figure 6. Offset Adjustment Circuit
Figure 8. Gain Adjustment Circuit
–6
× 1200 ppm/°C
Rev. B | Page 6 of 12
An alternate gain adjust circuit which contributes negligible
gain tempco if metal film resistors (Tempco < 100 ppm/°C) are
used is shown in Figure 9.
THEORY OF OPERATION
On receipt of a CONVERT START command, the AD ADC
AD ADC85 converts the voltage as its analog input into an
equivalent 12-bit binary number. This conversion is
accomplished as follows: The 12-bit successive approximation
register (SAR) has its 12-bit outputs connected both to the
device bit output pins and to the corresponding bit inputs of the
feedback DAC. The analog input is successively compared to t
feedback DAC output, one bit at a time (MSB first, LSB last).
The decision to keep or reject each bit is then made at the
completion of each bit comparison p
state of the
TIMING
The timing diagram is shown in Figure 10. Receipt of a
CONVERT START signal sets the STATUS flag, indicating
conversion in progress. This, in turn, removes the inhibit
applied to the gated clock, permitting it to run through 13
cycles. All the SAR parallel bits, STATUS flip-flops, and the
gated clock inhibit signal are initialized on the trailing edge of
the CONVERT START signal. At time t
to Bit 12 are set unconditionally. At t
(keep) and Bit 2 is unconditionally reset. At t
is made (keep) and Bit 3 is reset unconditionally. This sequence
continues until the Bit 12 (LSB) decision (keep) is made at t
After a 40 ns delay period, the STATUS flag is reset, indicating
that the conversion is complete and that the parallel output d
is valid. Resetting the STATUS flag restores the gated clock
inhibit signal, forcing the clock output to the Logic 0 state.
Corresponding parallel data bits become v
positive-going clock edge (see Figure 10).
Incorporation of the 40ns delay guarantees that the parallel da
is valid at the Logic 1 to 0 transition of the STATUS flag,
permitting parallel data transf
e
dge of the STATUS signal.
comparator at that time.
Figure 9. Low Tempco G ain Adjustment Circuit
er to be initiated by the trailing
1
eriod, depending on the
, the Bit 1 decision is made
0
, Bit 1 is reset and Bit 2
alid on the same
2
, the Bit 2 decision
12
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