uda1320ats NXP Semiconductors, uda1320ats Datasheet - Page 5

• Manufacturer Part Number: uda1320ats
• Description: Low-cost Stereo Filter Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
2000 Jan 10
handbook, halfpage
BCK
WS
DATAI
V
V
SYSCLK
APPSEL
APPL3
APPL2
APPL1
APPL0
V
V
V
V
V
SYMBOL
DDD
SSD
REF(DAC)
DDA
O(L)
SSA
O(R)
Low-cost stereo filter DAC
PINNING
SYSCLK
APPSEL
APPL3
DATAI
V DDD
V SSD
PIN
10
11
12
13
14
15
16
BCK
1
2
3
4
5
6
7
8
9
WS
Fig.2 Pin configuration.
bit clock
word select
data input
digital power supply
digital ground
system clock: 256f
application mode select
application pin 3
application pin 2
application pin 1
application pin 0
DAC reference voltage
analog supply voltage
left output voltage
analog ground
right output voltage
1
2
3
4
5
6
7
8
UDA1320A
MGM817
DESCRIPTION
16
15
14
13
12
11
10
9
V O(R)
V SSA
V O(L)
V DDA
V REF(DAC)
APPL0
APPL1
APPL2
s
, 384f
s
, 512f
s
5
8
8.1
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
The options are 256f
and 256f
must be locked in frequency to the digital interface input
signals.
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
8.2
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = V
two static modes (APPSEL = 0.5V
APPSEL = V
functions (active = HIGH).
Table 1 Selection modes via APPSEL (note 1)
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
In L3 mode pin APPL0 must be set to LOW.
APPL0
APPL1
APPL2
APPL3
PIN
FUNCTIONAL DESCRIPTION
System clock
Application modes
s
plus 384f
TEST
L3CLOCK
L3MODE
L3DATA
DDD
V
). See Table 1 for APPL0 to APPL3 pin
SSD
s
for the static mode. The system clock
s
, 384f
MUTE
DEEM
SF0
SF1
s
and 512f
APPSEL
0.5V
(384f
Preliminary specification
DDD
UDA1320ATS
DDD
s
)
s
or
for the L3 mode
SSD
) or to either of
MUTE
DEEM
SF0
SF1
(256f
V
DDD
s
)