tda9898hn/v2 NXP Semiconductors, tda9898hn/v2 Datasheet - Page 35

• Manufacturer Part Number: tda9898hn/v2
• Description: Tda9897; Tda9898 Multistandard Hybrid If Processing
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 44.
[1]
Table 45.
Table 46.
TDA9897_TDA9898_3
Product data sheet
Bit
EASY3
W8[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit
7
6
5
4 to 0
DAGCSLOPE
Access to register W1 to W6 after selection of an easy setting mode would require a transfer of all W1 to W6 register data.
7
EASY2
W8[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Easy setting (to be used for fixed bit set-up only)
W9 - data write register bit allocation
W9 - data write register bit description
Symbol
DAGCSLOPE
TAGCIS
TAGCTC
TOPNEG[4:0]
TAGCIS
EASY1
W8[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
6
Description
AGCDIN input characteristic; see
tuner AGC IF input
tuner AGC time constant
TOP adjustment for integral loop mode; see
TAGCTC
EASY0
W8[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 = high voltage for high gain
0 = low voltage for high gain
1 = inverse to VIF input
0 = aligned to VIF input
1 = 2nd mode
0 = normal
5
Mode or
standard
off
-
-
-
-
I 6.0
B/G 5.5
direct IF
M Japan 4.5
LIF 6/36
-
D/K 6.5
radio 5.5
-
L 6.5
-
TOPNEG4
Rev. 03 — 11 January 2008
4
Name
-
-
-
-
-
ES2
ES3
ES4
ES5
ES6
-
ES8
ES9
-
ES11
-
TOPNEG3
[1]
Figure 45
3
Bit definition (hexadecimal)
W1
-
-
-
-
-
58
38
08
18
28
-
78
BB
-
79
-
Table 47
TDA9897; TDA9898
TOPNEG2
W2
-
-
-
-
-
B1
B1
E1
F1
88
-
B1
B8
-
33
-
Multistandard hybrid IF processing
2
W3
-
-
-
-
-
CC
4C
64
44
60
-
4C
40
-
00
-
TOPNEG1
W4
-
-
-
-
-
60
60
62
73
61
-
70
26
-
60
-
1
W5
-
-
-
-
-
80
40
00
00
AD
-
C0
6B
-
C0
-
© NXP B.V. 2008. All rights reserved.
W6
-
-
-
-
-
80
80
81
80
00
-
80
00
-
C0
-
TOPNEG0
35 of 103
0
W7
-
-
-
-
-
0C
0C
08
08
0C
-
0C
04
-
0C
-