as8510 austriamicrosystems, as8510 Datasheet - Page 18

• Manufacturer Part Number: as8510
• Description: Data Acquisition Device For Battery Sensors
• Manufacturer: austriamicrosystems

AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.3 Digital Implementation of Measurement Path
Figure 3. Block Diagram of Digital Implementation
Figure 3
density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock (MOD_CLK).
The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one of 2kHz or
4kHz selected by Register CLK_REG in
first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I, DECREG_R1_V in
The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the CIC2 filter with a decimation
ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter. FIR Filter is provided to offer
matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide averaged output and the
number of samples for averaging can be any integer value from 1 to 15.
7.4 Modes of Operation
The device operates in four different modes, namely,
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be
carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on
the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the
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Normal Mode 1 (NOM1),
Normal Mode 2 (NOM2),
Standby Mode 1 (SBY1), and,
Standby Mode 2 (SBY2).
shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit pulse
MOD_CLK
MOD_IN
f
mod
64 / 128
CIC1
R1
Table
CHP_CLK
MOD_CLK
f
33. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase process. In the
mod
/ R1
Dechopper
f
chop
CLK DIVISION
BLOCK
f
chop
R1
Revision 3.4
* 2
CIC2
R2
f
chop
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
* 2 / R2
FIR_MA_SEL
FIR/MA
Figure
f
chop
* 2 / R2
4.
DATAOUT
Table
18 - 46
33.