adv7189b Analog Devices, Inc., adv7189b Datasheet - Page 16

• Manufacturer Part Number: adv7189b
• Description: Multiformat Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

ADV7189B
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F[2]
The digital core of the ADV7189B can be shut down by using a
pin ( PWRDN ) and a bit ( PWRDN , see below). The PDBP con-
trols which of the two has the higher priority. The default is to
give the pin ( PWRDN ) priority. This allows the user to have the
ADV7189B powered down by default.
When PDBD is 0 (default), the digital core power is controlled
by the PWRDN pin (the bit is disregarded).
When PDBD is 1, the bit has priority (the pin is disregarded).
PWRDN, Address 0x0F[5]
Setting the PWRDN bit switches the ADV7189B into a chip-
wide power-down mode. The power down stops the clock
from entering the digital section of the chip, thereby freezing
its operation. No I
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I
and remains operational in power-down mode.
The ADV7189B leaves the power-down state if the PWRDN bit
is set to 0 (via I
RESET pin.
Note: PDBP must be set to 1 for the PWRDN bit to power down
the ADV7189B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7189B is in chip-wide power down.
ADC Power-Down Control
The ADV7189B contains three 12-bit ADCs (ADC 0, ADC 1,
and ADC 2). If required, it is possible to power down each ADC
individually.
The ADCs should be powered down when in:
x
x
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
S-Video mode. ADC 2 should be powered down to save on
power consumption.
2
C), or if the overall part is reset using the
2
C bits are lost during power down. The
2
C interface itself is unaffected,
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PWRDN_ADC_0, Address 0x3A[3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
PWRDN_ADC_1, Address 0x3A[2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A[1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Chip Reset (RES), Address 0x0F[7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7189B, issues a full chip reset. All I
their default values. Note: Some register bits do not have a reset
value specified. They keep their last written value. These bits are
marked as having a reset value of x in the register table. After
the reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the RES bit, or initiating a reset via the pin, the
part returns to the default mode of operation with respect to
its primary mode of operation. All I
their default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However,
it is recommended to wait 5 ms before any further I
performed.
The I
tion on the ninth clock cycle when chip reset is implemented.
See the
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
2
C master controller receives a no-acknowledge condi-
M PU Port Description section for a full description.
1 4 7 H
2
C bits are loaded with
2
C registers get reset to
2
C writes are