adv7189b Analog Devices, Inc., adv7189b Datasheet - Page 23

• Manufacturer Part Number: adv7189b
• Description: Multiformat Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
x
x
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
FSCLE F
The FSCLE bit allows the user to choose whether the status
of the color subcarrier loop is taken into account when the
overall lock status is determined and presented via Bits[1:0]
in Status Register 1. This bit must be set to 0 when operating
the ADV7189B in YPrPb component mode in order to generate
a reliable HLOCK status bit.
Setting FSCLE to 0 (default) makes the overall lock status
dependent on only the horizontal sync lock.
Setting FSCLE to 1 makes the overall lock status dependent on
the horizontal sync lock and F
VS_Coast[1:0], Address 0xF9[3:2]
These bits are used to set VS free-run (coast) frequency.
Table 19. VS_COAST[1:0] Function
VS_COAST[1:0]
00 (default)
01
10
11
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0[1:0]. It counts
the value in lines of video.
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video.
It reacts quickly.
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
SC
Lock Enable, Address 0x51[7]
Description
Auto coast mode—follows VS
frequency from last video input
Forces 50 Hz coast mode
Forces 60 Hz coast mode
Reserved
SC
lock.
Rev. B | Page 23 of 104
Table 20. CIL Function
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into unlocked state, and reports this via Status 0[1:0]. It counts
the value in lines of video.
Table 21. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
SD COLOR CONTROLS
These registers allow the user to control picture appearance
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamp-
ing, although both controls affect the signal’s dc level.
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This register allows the user to adjust the contrast of the picture.
Table 22. CON Function
CON[7:0]
0x80 (default)
0x00
0xFF
SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address
0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only. The user can adjust the saturation of the picture.
Table 23. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
Description
1
2
5
10
100
500
1000
100000
Chroma gain = 0 dB
Gain on Cb channel = +6 dB
Description
Gain on Cb channel = −42 dB
Description
1
2
5
10
100
500
1000
100000
ADV7189B