adv7189b Analog Devices, Inc., adv7189b Datasheet - Page 67

• Manufacturer Part Number: adv7189b
• Description: Multiformat Sdtv Video Decoder
• Manufacturer: Analog Devices, Inc.

Register Name
SD Offset Cb
SD Offset Cr
SD Saturation
Cb
SD Saturation
Cr
NTSC V Bit
Begin
NTSC V Bit End
NTSC F Bit
Toggle
PAL V Bit Begin
PAL V Bit End
PAL F Bit Toggle
Reserved
Drive Strength
Reserved
IF Comp Control
VS Mode
Control
I
The following registers are located in the Common
Table 84. Interrupt (Page 2) Register Map Details
Register Name
Interrupt Config 0
Reserved
Interrupt Status 1
Interrupt Clear 1
Interrupt Mask b1
Reserved
Interrupt Status 2
Interrupt Clear 2
Interrupt Mask b2
Raw Status 3
Interrupt Status 3
Interrupt Clear 3
Interrupt Mask b3
1
2
P
To access the interrupt register map, the register access page[1:0] bits in register address 0x0E must be programmed to 01b.
C REGISTER MAP DETAILS
P
Bit 7
SD_OFF_CB.7
SD_OFF_CR.7
SD_SAT_CB.7
SD_SAT_CR.7
NVBEGDEL O
NVENDDEL O
NFTOGDEL O
PVBEGDEL O
PVENDDEL O
PFTOGDEL O
Reset
Value
0001
x000
x000
0000
x000
0000
0xxx
0000
0xxx
0000
xx00
0000
xx00
0000
rw
rw
r
w
rw
r
w
rw
r
r
w
rw
Bit 6
SD_OFF_CB.6
SD_OFF_CR.6
SD_SAT_CB.6
SD_SAT_CR.6
NVBEGDEL E
NVENDDEL E
NFTOGDEL E
PVBEGDEL E
PVENDDEL E
PFTOGDEL E
Subaddress
Dec
64
65
66
67
68
69
70
71
72
73
74
75
76
Hex
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
Bit 5
SD_OFF_CB.5
SD_OFF_CR.5
SD_SAT_CB.5
SD_SAT_CR.5
NVBEGSIGN
NVENDSIGN
NFTOGSIGN
PVBEGSIGN
PVENDSIGN
PFTOGSIGN
DR_STR.1
7
INTRQ_DU
R_SEL.1
MPU_STIM
_INTRQ_Q
MPU_STIM
_INTRQ_
CLR
MPU_
STIM_INTR
Q_MSKB
I 2C Register Maps and Register Access sections, Page 2.
2 5 9 H
8 F
1
6
INTRQ_
DUR_SEL.0
MV_PS_
CS_Q
MV_PS_
CS_CLR
MV_PS_
CS_MSKB
Rev. B | Page 67 of 104
Bit 4
SD_OFF_CB.4
SD_SAT_CR.4
NVEND.4
NFTOG.4
PVEND.4
DR_STR.0
SD_OFF_CR.4
SD_SAT_CB.4
NVBEG.4
PVBEG.4
PFTOG.4
5
MV_INTRQ
_SEL.1
SD_FR_
CHNG_Q
SD_FR_CH
NG_CLR
SD_FR_CH
NG_MSKB
PAL_SW_LK
_CHNG_Q
PAL_SW_L
K_CHNG_
CLR
PAL_SW_
LK_CHNG_
MSKB
Bit 3
SD_OFF_CB.3
SD_OFF_CR.3
SD_SAT_CB.3
SD_SAT_CR.3
NVBEG.3
NVEND.3
NFTOG.3
PVBEG.3
PVEND.3
PFTOG.3
DR_STR_C.1
VS_COAST_
MODE.1
4
MV_INTRQ
_SEL.0
SCM_LOCK
SCM_LOCK
_CHNG_Q
SCM_LOCK
_CHNG_
CLR
SCM_LOCK
_CHNG_
MSKB
Bit 2
SD_OFF_CB.2
SD_OFF_CR.2
SD_SAT_CB.2
SD_SAT_CR.2
NVBEG.2
NVEND.2
NFTOG.2
PVBEG.2
PVEND.2
PFTOG.2
DR_STR_C.0
IFFILTSEL.2
VS_COAST_
MODE.0
3
WSS_CHN
GD_Q
WSS_
CHNGD_
CLR
WSS_
CHNGD_
MSKB
SD_AD_
CHNG_Q
SD_AD_CH
NG_CLR
SD_AD_
CHNG_
MSKB
2
MPU_STIM
_INTRQ
CGMS_
CHNGD_Q
CGMS_
CHNGD_
CLR
CGMS_
CHNGD_
MSKB
SD_H_LOCK
SD_H_LOCK
_CHNG_Q
SD_H_
LOCK_
CHNG_CLR
SD_H_
LOCK_
CHNG_MSKB
Bit 1
SD_OFF_CB.1
SD_OFF_CR .1
SD_SAT_CB.1
SD_SAT_CR.1
NVBEG.1
NVEND.1
NFTOG.1
PVBEG.1
PVEND.1
PFTOG.1
DR_STR_S.1
IFFILTSEL.1
EXTEND_VS_
MIN_FREQ
1
INTRQ_OP
_SEL.1
SD_
UNLOCK_Q
SD_UNLOCK
_CLR
SD_UNLOCK
_MSKB
GEMD_Q
GEMD_CLR
GEMD_
MSKB
SD_V_LOCK
SD_V_LOCK
_CHNG_Q
SD_V_LOCK
_CHNG_
CLR
SD_V_
LOCK_
CHNG_MSKB
ADV7189B
Bit 0
SD_OFF_CB.0
SD_OFF_CR.0
SD_SAT_CB.0
SD_SAT_CR.0
NVBEG.0
NVEND.0
NFTOG.0
PVBEG.0
PVEND.0
PFTOG.0
DR_STR_S.0
IFFILTSEL.0
EXTEND_VS_
MAX_FREQ
SD_OP_
CHNG_CLR
0
INTRQ_OP
_SEL.0
SD_LOCK_
Q
SD_LOCK_
CLR
SD_LOCK_
MSKB
CCAPD_Q
CCAPD_
CLR
CCAPD_
MSKB
50HZ
SD_OP_
CHNG_Q
SD_OP_
CHNG_MSKB
SD_OP_