adv7322 Analog Devices, Inc., adv7322 Datasheet - Page 26

• Manufacturer Part Number: adv7322
• Description: Multiformat 11-bit Hdtv Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7322
REGISTER ACCESS
The MPU can write to or read from all of the registers of the
ADV7322 except the subaddress registers, which are write only
registers. The subaddress register determines which register the
next read or write operation will access. All communications
with the part through the bus start with an access to the
subaddress register. A read/write operation is then performed
from/to the target address, which increments to the next
address until a stop command is performed on the bus.
Table 7. Registers 0x00 to 0x01
SR7–
SR0
0x00
0x01
Register
Power
Mode
Register
Mode
Select
Register
Bit Description
Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal PLL
cct are disabled. I
registers can be read from
and written to in sleep
mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the oversampling to be
switched off.
DAC F: Power On/Off.
DAC E: Power On/Off.
DAC D: Power On/Off.
DAC C: Power On/Off.
DAC B: Power On/Off.
DAC A: Power On/Off.
Reserved
Clock Edge.
Reserved.
Clock Align.
Input Mode.
Y/C/S Bus Swap.
2
C
Bit 7
0
1
0
1
Bit 6
0
1
0
0
0
0
1
1
1
1
Bit 5
0
1
0
0
1
1
0
0
1
1
Rev. PrA | Page 26 of 88
Bit 4
0
1
0
1
0
1
0
1
0
1
Bit 3
0
1
0
1
REGISTER PROGRAMMING
The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The communication register is an 8-bit write-only register. After
the part is accessed over the bus and a read/write operation is
selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
Bit 2
0
1
0
Bit 1
0
1
0
1
Bit 0
0
1
0
Preliminary Technical Data
Register Setting
Sleep mode off.
Sleep mode on.
PLL on.
PLL off.
DAC F off.
DAC F on.
DAC E off.
DAC E on.
DAC D off.
DAC D on.
DAC D off.
DAC C on.
DAC B off.
DAC B on.
DAC A off.
DAC A on.
Reserved
Cb clocked on rising
edge.
Y clocked on rising edge
Must be set if the phase
delay between the two
input clocks is
<9.25 ns or >27.75 ns.
SD input only.
PS input only.
HDTV input only.
SD and PS [16-bit].
SD and PS [8-bit].
SD and HDTV [SD
oversampled].
SD and HDTV [HDTV
oversampled].
PS only [at 54 MHz].
Allows data to be
applied to data ports in
various configurations
(SD feature only).
Reg. Reset
Values
(Shaded)
0xFC
Only for PS
interleaved
input at 27 MHz.
Only if two
input clocks are
used.
0x38
See Table 21.