xc2c128 Xilinx Corp., xc2c128 Datasheet
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xc2c128
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xc2c128 Summary of contents
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... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS093 (v3.2) March 8, 2007 Product Specification 0 XC2C128 CoolRunner-II CPLD Product Specification 0 0 Description The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications ...
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... LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL make use compliance. CoolRunner-II CPLDs are also 1.5V I/O com- patible with the use of Schmitt-trigger inputs. Table 1). This Table 1: I/O Standards for XC2C128 IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 ...
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... CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO www.xilinx.com XC2C128 CoolRunner-II CPLD Value Units –0.5 to 2.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –0.5 to 4.0 V –65 to +150 °C + 150 ° ...
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... XC2C128 CoolRunner-II CPLD LVCMOS and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter V Input source voltage ...
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... Test Conditions –8 mA CCIO mA CCIO , also peak to peak ac noise on V CCIO REF of receiving devices. REF Test Conditions V www.xilinx.com XC2C128 CoolRunner-II CPLD Min. Max. 0.4 = 1.4V 0.2 Min. Max. 1.4 3 CCIO CCIO 0 0 CCIO CCIO Min. Typ. Max. ...
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... XC2C128 CoolRunner-II CPLD Symbol Parameter V High level output voltage OH V Low level output voltage OL Notes should track the variations in V REF transmitting device must track Test Conditions I = – CCIO mA 1.7V OL CCIO , also peak to peak ac noise on V ...
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... OR array (one counter per function block). SYSTEM2 the maximum external frequency using one p-term while F EXT1 SU1 CO 4. Typical configuration current during DS093 (v3.2) March 8, 2007 Product Specification Parameter mA. CONFIG www.xilinx.com XC2C128 CoolRunner-II CPLD -6 -7 Min. Max. Min. Max. - 5.7 - 7.0 - 6.0 - 7.5 3 ...
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... XC2C128 CoolRunner-II CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Direct data register input delay DIN T Global Clock buffer delay GCK T Global set/reset buffer delay GSR T Global 3-state buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay ...
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... Figure 2: Derating Curve for T DS093 (v3.2) March 8, 2007 Product Specification (1) Min DIN GCK GSR - OUT , DIN GCK GSR - OUT , DIN GCK GSR - OUT Switching Test Conditions 8 16 DS093_02_050103 PD www.xilinx.com XC2C128 CoolRunner-II CPLD -6 -7 Max. Min. Max. 0.6 - 0.7 1.5 - 3.0 0.8 - 0.9 3.0 - 4.0 0.5 - 0.6 1.2 - 3.0 1.2 - 1.4 3.0 - 4.0 0.8 - 2.5 0.5 - 0.5 0.8 - 2.5 0.5 - 0.5 2.0 - 2.5 0.0 - 0.0 Figure 3: AC Load Circuits ...
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... VO (Output Volts) Figure 4: Typical I/V Curves for XC2C128 Pin Descriptions (Continued) Function I/O Block Bank ...
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... www.xilinx.com XC2C128 CoolRunner-II CPLD Macro- cell VQ100 CP132 TQ144 1 65 G13 G12 F14 F13 F12 E13 100 7 70 E12 101 ...
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... XC2C128 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell VQ100 CP132 TQ144 Pin Descriptions (Continued) I/O Function Bank Block C12 ...
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... R XC2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type TCK TDI TDO TMS V (JTAG supply voltage) CCAUX Power internal ( Power Bank 1 I CCIO1 Power Bank 2 I CCIO2 Ground No connects Total user I/O (including dual function pins) Notes: 1. Pin compatible with all larger and smaller densities except where I/O banking is used. ...
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... Thin Quad Flat Pack 47.5 12.5 Very Thin Quad Flat Pack; Pb-free 72.4 15.7 Chip Scale Package; Pb-free 46.1 7.9 Thin Quad Flat Pack; Pb-free = –40° +85° C). A Pb- Free Example: XC2C128 144 C Device Speed Grade Package Type Pb -Free Number of Pins Temperature Range R XC2Cxxx TQ144 Package 7C Speed ...
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... DS093 (v3.2) March 8, 2007 Product Specification VQ100 12 Top View Figure 6: VQ100 Very Thin Quad Flat Pack www.xilinx.com XC2C128 CoolRunner-II CPLD GND 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 GND 69 I I/O I I/O I GND 61 I/O 60 ...
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... XC2C128 CoolRunner-II CPLD P VCC I/O(5) I/O GND I/O(2) I I/O(4) I I/O( I/O GND I/O(2) K I/O I/O VCCIO1 J H I/O I/O I/O G I/O I/O I/O I/O I/O I/O F I/O I/O I I/O I/O VAUX C I/O I/O(1) I/O(1) VCCIO2 B I/O I/O(1) GND I/O(1) VCC I/O( VCCIO1 GND I/O I/O I/O I/O NC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O TDI CP132 Bottom View I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO VCCIO2 I/O I/O I/O I/O GND Figure 7: CP132 Chip Scale Package www.xilinx.com VCCIO1 I/O I/O I/O I/O TMS I/O GND I/O I/O I/O TCK I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND I/O I/O GND ...
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... AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS093 (v3.2) March 8, 2007 Product Specification TQ144 Top View Figure 8: TQ144 Thin Quad Flat Pack www.xilinx.com XC2C128 CoolRunner-II CPLD GND 108 NC 107 NC 106 I/O 105 ...
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... XC2C128 CoolRunner-II CPLD Additional Information Additional information is available for the following CoolRunner-II topics: • XAPP784: Bulletproof CPLD Design Practices • XAPP375: Timing Model • XAPP376: Logic Engine • XAPP378: Advanced Features • XAPP382: I/O Characteristics • XAPP389: Powering CoolRunner-II • XAPP399: Assigning VREF Pins Revision History The following table shows the revision history for this document ...