xcr3064xl Xilinx Corp., xcr3064xl Datasheet
xcr3064xl
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xcr3064xl Summary of contents
Page 1
... Preliminary Product Specification 0 14 Description The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of four logic blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. ...
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... XCR3064XL 64 Macrocell CPLD 35.0 30.0 25.0 20.0 15.0 10.0 Table 1: I vs. Frequency ( Frequency (MHz Typical I (mA Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter V Output High voltage for 3.3V outputs OH V Output Low voltage for 3.3V outputs OL I Input leakage current IL I I/O High-Z leakage current IH I Standby current ...
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... See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. Typical current draw during configuration 3.6V. 5. Output pF. L DS017 (v1.1) August 30, 2000 Preliminary Product Specification -6 Min. Max. - 5.5 (3) - 6.0 - 4.0 2 2 145 - 20.0 - 7.5 (5) - 7.5 - 6.5 - 8.0 www.xilinx.com 1-800-255-7778 XCR3064XL 64 Macrocell CPLD (1,2) -7 -10 Min. Max. Min. Max. - 7.0 - 9.1 - 7.5 - 10.0 5.0 - 6.5 2.5 - 3.0 - 4 3.0 - 4.0 - 5 119 - ...
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... XCR3064XL 64 Macrocell CPLD Timing Model The XPLA3 architecture follows a simple timing model that allows deterministic timing in design and redesign. The basic timing model is shown in Figure the XPLA3 CPLD is the ability to have product term inputs into a single macrocell and maintain consistent tim- ing ...
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... Time Adders T Fold-back NAND delay LOGI3 T Universal delay UDA T Slew rate limited delay SLEW DS017 (v1.1) August 30, 2000 Preliminary Product Specification -6 -7 Min. Max. Min 1.3 - 1.0 - 1.0 4.0 - 5.5 2.0 - 2.5 3.0 - 4 4.0 - www.xilinx.com 1-800-255-7778 XCR3064XL 64 Macrocell CPLD -10 Max. Min. Max. Unit 1.6 - 2.2 ns 2.5 - 3.1 ns 1.0 - 1.3 ns 2.7 - 3.6 ns 5.0 - 5.7 ns 1.6 - 2 1.3 - 1.6 ns 2.3 - 2.1 ns 5.0 - 6.0 ns 2.7 - 3.3 ns 3.2 - 4.2 ns 2.9 - 3.5 ns 7.5 - 9.5 ns 2 ...
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... XCR3064XL 64 Macrocell CPLD Switching Characteristics 5.6 5.5 5.4 5.3 5.2 5.1 5.0 4 Number of Adjacent Outputs Switching Figure 4: Derating Curve for T 6 Component OUT Measurement T POE (High) T POE (Low Note: For T POD Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified ...
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... ( DS017 (v1.1) August 30, 2000 Preliminary Product Specification Table 2: XCR3064XL Pin Descriptions (Continued) Function Block C CP56 VQ100 A10 ...
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... XCR3064XL 64 Macrocell CPLD Table 3: X36CR3064XL Global, JTAG, Port Enable, Power, and No connect Pins Pin Type VQ44 IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN V 9, 17, 29 GND 16, 24 Connects Notes: 1. Port Enable is brought Low to enable JTAG pins when JTAG pins are used as I/O. See family data sheet for more information. ...
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... R Ordering Information Example: XCR3064XL - Device Type Speed Grade Speed Options -10 pin-to-pin delay -7: 7.5 ns pin-to-pin delay -6: 6.0 ns pin-to-pin delay Component Availability Pins Type Plastic VQFP Code XCR3064XL -6 -7, -10 Revision History The following table shows the revision history for this document.. ...