xa95144xl-15vqg64q Xilinx Corp., xa95144xl-15vqg64q Datasheet
xa95144xl-15vqg64q
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xa95144xl-15vqg64q Summary of contents
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... Slew rate control on individual outputs for reducing EMI generation • Refer to XC9500XL Family data sheet (DS054) for architecture description • Refer to XA9536XL data sheet (DS598), the XA9572XL data sheet (DS599), and the XA95144XL data sheet (DS600) for pin tables Table 1: XA9500XL Device Family Device Temperature Grade XA9536XL I, Q ...
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... XA9500XL Automotive CPLD Product Family Table 2: XA9500XL Packages and User I/O Pins (not including four dedicated JTAG pins) Device VQG44 XA9536XL 34 XA9572XL 34 XA95144XL -- Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage relative to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) ...
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... Device Ordering Options Device Speed XA9536XL -15 15.5 ns pin-to-pin delay XA9572XL XA95144XL XA9500XL Automotive Requirements and Recommendations Requirements The following requirements are for all automotive applica- tions: 1. All automotive customers are required to keep the Macrocell Power selection set to low, and the Logic Optimization set to density when designing with ISE software ...
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XA9500XL Automotive CPLD Product Family 7. Do not drive I/Os pins above the V I/O bank. a. The current flow can go into V voltage regulator can also increase undesired leakage current associated with the device ...
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R Warranty Disclaimer THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF ...