adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet
adsp-21371kswz-2a
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adsp-21371kswz-2a Summary of contents
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... High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory, ADSP-21371—1M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM On-chip memory, ADSP-21375—0.5M bit of on-chip SRAM and a dedicated 2M bit of on-chip mask-program- ...
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... Outputs of PCGs A and B can be routed through DAI pin Outputs of PCGs C and D can be driven on to DAI as well as DPI pins 8 dual data line serial ports (ADSP-21371) that operate Mbps on each data line — each has a clock, frame sync, and two data lines that can be configured as either a ...
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... ADSP-21371/ADSP-21375 Family Core Architecture .....4 ADSP-21371/ADSP-21375 Memory ...........................6 External Memory ...................................................6 ADSP-21371/ADSP-21375 Input/Output Features .........8 System Design ..................................................... 11 Development Tools .............................................. 11 Additional Information ......................................... 12 Pin Function Descriptions ........................................ 13 Data Modes, ADSP-21371 ...................................... 15 Boot Modes ........................................................ 15 Core Instruction Rate to CLKIN Ratio Modes ............. 15 ADSP-21371/ADSP-21375 Specifications ..................... 16 Operating Conditions ........................................... 16 Electrical Characteristics ........................................ 16 Absolute Maximum Ratings ................................... 17 Maximum Power Dissipation ................................. 17 Package Information ...
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... SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21371/ ADSP-21375 are source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs as well as with first gener- ation ADSP-2106x SHARC processors in SISD (single- instruction, single-data) mode. The ADSP-21371/ADSP-21375 ...
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... The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15 ...
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... In this case, the instruction must be available in the cache. The ADSP-21371’s SRAM can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bit data, 21.3k words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words ...
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... Table 4. External Memory Execution In the ADSP-21371/ADSP-21375, the program sequencer can execute code directly from external memory bank 0 (SRAM, SDRAM). This allows a reduction in internal memory size, thereby reducing the die area. With external execution, pro- grams run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus coupled with the inherent latency of fetching instructions from SDRAM ...
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... IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Thirty-two channels of DMA are available on the ADSP-21371, 16 via the serial ports, eight via the input data port, two for the UART, two for the SPI interface, two for the external port, and two for memory-to-memory transfers ...
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... For the ADSP-21371, the DAI also includes eight serial ports, four precision clock generators (PCG), and an input data port (IDP). For the ADSP-21375, the DAI also includes four serial ports, four precision clock (PCG) and an input data port (IDP). The IDP provides an additional input path to the core of the ...
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... In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21371/ADSP-21375 processors have a total of three timers: a core timer that can generate periodic software inter- rupts and two general purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21371/ ADSP-21375 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product ...
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... Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21371/ ADSP-21375 architecture and functionality. For detailed infor- mation on the ADSP-21371/ADSP-21375 family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Programming Reference ...
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... External Data. The data pins can be multiplexed to support the external memory interface pulled high data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0–3) pins will be in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the DATA for parallel input data ...
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... ADSP-21371/ADSP-21375. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21371/ADSP-21375. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21371/ADSP-21375 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ ...
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... These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors. DATA MODES, ADSP-21375 For the ADSP-21375, the 16 data pins of the external memory ...
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... Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU. 8 Typical internal current data reflects nominal operating conditions. 9 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information. 10 Applies to all signal pins. 11 Guaranteed, but not tested. ...
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... MAXIMUM POWER DISSIPATION provides details about See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for detailed Ordering thermal and power information regarding maximum power dis- sipation. For information on package thermal specifications, see ...
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... Figure 3 external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP- 2136x SHARC Processor Programming Reference < < ...
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... Note the definitions of various clock periods shown in which are a function of CLKIN and the appropriate ratio con- trol shown in Table 13. Table 13. ADSP-21371/ADSP-21375 CLKIN and CCLK Clock Generation Operation Timing Requirements Description Calculation CLKIN Input Clock 1/t CCLK Core Clock 1/t Table 14. Clock Periods Timing ...
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... ADSP-21371/ADSP-21375 Power-Up Sequencing The timing requirements for processor startup are given in Table 15. Table 15. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V DDINT IVDDEVDD 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST ...
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... CK CLKIN t CKH Figure 5. Clock Input Clock Signals The ADSP-21371/ADSP-21375 can use an external clock or a crystal. See the CLKIN pin description in mer can configure the ADSP-21371/ADSP-21375 to use its internal clock generator by connecting the necessary compo- nents to CLKIN and XTAL. Figure 6 shows the component connections used for a crystal operating in fundamental mode ...
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... ADSP-21371/ADSP-21375 Reset Table 17. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming ...
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... Table 19. Core Timer Parameter Switching Characteristic t CTIMER Pulse Width WCTIM FLAG3 (CTIMER) Min SRUNRST t WRUNRST Figure 8. Running Reset Min 4 × t – 1 PCLK t WCTIM Figure 9. Core Timer Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit ns ns Max Unit ns ...
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... ADSP-21371/ADSP-21375 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20 DPI_P14 1 pins when they are configured as interrupts. – Table 20. Interrupts Parameter Timing Requirement t IRQx Pulse Width ...
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... Delay DAI/DPI Pin Input Valid to DAI Output Valid DPIO Min 2 × t PCLK t PWI Figure 12. Timer Width Capture Timing DAI_Pn DPI_Pn DAI_Pm DPI_Pm t DPIO Figure 13. DAI Pin to Pin Direct Routing Rev Page June 2008 ADSP-21371/ADSP-21375 Max 31 2 ×(2 – 1) × t PCLK Min Max 1.5 10 Unit ns Unit ns ...
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... DTRIGCLK t PCG Frame Sync Delay After PCG Trigger DTRIGFS 1 t Output Clock Period PCGOW D = FSxDIV FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock Generators” chapter. 1 Normal mode of operation. t STRIG DAI_Pn DPI_Pn ...
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... DPI_P14–1, DATA31–0, FLAG3–0 FOPW DPI_P14 (FLAG3 (DATA31 DPI_P14 (FLAG3 (DATA31 Table 6 on Pulse Width IN Pulse Width OUT - FIPW - OUT - 0) t FOPW Figure 15. Flags Rev Page June 2008 ADSP-21371/ADSP-21375 Min Max 2 × PCLK 2 × t – 2 PCLK Unit ns ns ...
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... ADSP-21371/ADSP-21375 SDRAM Interface Timing Maximum SDRAM frequency for 1 133 MHz SDCLK. 1 Table 26. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before SDCLK SSDAT t DATA Hold After SDCLK HSDAT Switching Characteristics t SDCLK Period SDCLK t SDCLK Width High SDCLKH t SDCLK Width Low ...
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... SDCLK SDCLK , or t SDS. Test Conditions on Page 46 for the calculation of hold times given DRLD t DAD t DSAK Figure 17. Memory Read—Bus Master Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit – 5.12 ns SDCLK W – – 10 SCDCLK W – 7 ...
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... ADSP-21371/ADSP-21375 Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 28. Memory Write—Bus Master Parameter Timing Requirements t ACK Delay from Address, Selects ...
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... Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. 1.2 V, 266 MHz Min 2.5 2.5 2.5 2 Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit 10 ...
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... ADSP-21371/ADSP-21375 Table 31. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 32. Serial Ports—External Late Frame Sync ...
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... HFSI SFSI - DAI_P20 1 (FS) - DAI_P20 1 (DATA CHANNEL A/B) t DDTEN t DDTIN Figure 19. Serial Ports Rev Page June 2008 ADSP-21371/ADSP-21375 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t ...
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... ADSP-21371/ADSP-21375 DAI_P20 - 1 (SCLK) DAI_P20 - 1 (FS) DAI_P20 - 1 (DATA CHANNEL A/B) DAI_P20 - 1 (SCLK) DAI_P20 - 1 (FS) DAI_P20 - 1 (DATA CHANNEL A/B) NOTE: SERIAL PORT SIGNALS (SCLK, FS, USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20 THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN,NOT ROUTED DIRECTLY THROUGH SRU ...
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... DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. DAI_P20-1 (SCLK) DAI_P20-1 (FS) DAI_P20-1 (SDATA) Table 33. IDP 1.2 V, 266 MHz Min 3.8 2.5 2.5 2 SAMPLE EDGE t IDPCLK t IDPCLKW t t SISFS SIHFS t t SISD SIHD Figure 21. IDP Master Timing Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit ...
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... The timing requirements for the PDAP are provided in Table 34. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the PDAP chapter of the ADSP-21368 SHARC Processor Hardware Table 34. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... Pulse-Width Modulation Generators (PWM) For the ADSP-21371, the following timing specifications apply when the DATA31–16 pins are configured as PWM. Table 35. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Pulse-width modulation generator information does not apply to the ADSP-21375 ...
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... ADSP-21371/ADSP-21375 S/PDIF Transmitter For the ADSP-21371, serial data input to the S/PDIF transmitter 2 can be formatted as left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections pro- vide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 24 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
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... V, 266 MHz Min SITXCLKW t SITXCLK t SISCLKW t SISCLK t SISFS t SISD Figure 27. S/PDIF Transmitter Input Timing Min Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit SIHFS t SIHD Max Unit 73.8 MHz 49.2 MHz 192.0 kHz ...
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... ADSP-21371/ADSP-21375 S/PDIF Receiver For the ADSP-21371, the following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38. S/PDIF Receiver Internal Digital PLL Mode Timing ...
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... SPI Interface—Master The ADSP-21371/ADSP-21375 contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in Table 39 and Table 40 Table 39. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid To SPICLK Edge (Data Input Setup Time) ...
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... ADSP-21371/ADSP-21375 SPI Interface—Slave Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted, CPHASE=0 ...
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... DATA(5 8) STOP t RXD - DATA(5 8) STOP(1 t TXD Figure 31. UART Port—Receive and Transmit Timing Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit –1 ns PCLK –1 ns PCLK UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ - 2) UART TRANSMIT BIT SET BY PROGRAM; ...
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... ADSP-21371/ADSP-21375 TWI Controller Timing Table 42 and Figure 32 provide timing information for the TWI interface. Input Signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DPI_P14–1 pins. Table 42. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices ...
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... TDO SYSTEM INPUTS SYSTEM OUTPUTS Min TCK t t STAP HTAP t DTDO t t SSYS HSYS t DSYS Figure 33. IEEE 1149.1 JTAG Test Access Port Rev Page June 2008 ADSP-21371/ADSP-21375 Max Unit ...
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... SWEEP (V ) VOLTAGE (V) DDEXT Figure 34. ADSP-21371/ADSP-21375 Typical Drive at Junction Temperature TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 17 on Page 22 through Table 43 on Page output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage ...
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... LOAD CAPACITANCE (pF) Figure 39. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21371/ADSP-21375 processor is rated for perfor- mance over the temperature range specified in Conditions on Page 16. Table 44 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
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... ADSP-21371/ADSP-21375 208-LEAD LQFP_EP PINOUT Table 45. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Pin No. Signal Pin No DDINT 2 DATA28 54 3 DATA27 55 4 GND DDEXT 6 DATA26 58 7 DATA25 59 8 DATA24 60 9 DATA23 61 10 GND DDINT 12 DATA22 64 13 ...
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... Table 45. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Pin No. Signal Pin No. 45 DATA5 97 46 DATA2 98 47 DATA3 99 48 DATA0 100 49 DATA1 101 50 V 102 DDEXT 51 GND 103 52 V 104 DDINT Signal Pin No. Signal ADDR19 149 DAI5 ADDR20 150 V DDEXT ...
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... ADSP-21371/ADSP-21375 Table 46. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Pin No. Signal Pin No DDINT GND DDEXT GND DDINT ...
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... Table 46. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Pin No. Signal Pin No. 45 DATA5 97 46 DATA2 98 47 DATA3 99 48 DATA0 100 49 DATA1 101 50 V 102 DDEXT 51 GND 103 52 V 104 DDINT Signal Pin No. Signal ADDR19 149 DAI5 ADDR20 150 V DDEXT ...
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... AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE. Figure 40. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] ORDERING GUIDE Temperature Model Range 2 ADSP-21371KSWZ- + ADSP-21371KSWZ- + ADSP-21371BSWZ-2B - +85 C ...