adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 39

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in
DAI_P20
tions provided below are valid at the DAI_P20
Table 36. S/PDIF Transmitter Input Data Timing
1
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 37. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN
SISFS
SIHRS
SISD
SIHD
SITXCLKW
SITXCLK
SISCLKW
SISCLK
or any of the DAI pins.
Table
1
1
1
1
36. Input signals (SCLK, FS, SDATA) are routed to the
–
1 pins using the SRU. Therefore, the timing specifica-
SAMPLE EDGE
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Transmit Clock Width
Transmit Clock Period
Clock Width
Clock Period
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(TXCLK)
(SCLK)
(FS)
–
1 pins.
Figure 27. S/PDIF Transmitter Input Timing
t
SITXCLKW
Rev. B | Page 39 of 52 | June 2008
t
SISCLKW
t
t
SISCLK
SISFS
t
SISD
t
SITXCLK
1.2 V, 266 MHz
Min
3
3
3
3
9
20
36
80
Min
Max
ADSP-21371/ADSP-21375
t
t
SIHFS
SIHD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Max
73.8
49.2
192.0
Unit
MHz
MHz
kHz