adsp-21371kswz-2a Analog Devices, Inc., adsp-21371kswz-2a Datasheet - Page 18

• Manufacturer Part Number: adsp-21371kswz-2a
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371/ADSP-21375
TIMING SPECIFICATIONS
The ADSP-21371/ADSP-21375’s internal clock (a multiple of
CLKIN) provides the clock signal for timing internal memory,
processor core, and serial ports. During reset, program the ratio
between the processor’s internal clock frequency and external
(CLKIN) clock frequency with the CLKCFG1–0 pins (see
Table 10 on Page
The ADSP-21371/ADSP-21375’s internal clock switches at
higher frequencies than the system input clock (CLKIN). To
generate the internal clock, the processor uses an internal
phase-locked loop (PLL). This PLL-based clocking minimizes
the skew between the system clock (CLKIN) signal and the pro-
cessor’s internal clock.
Core clock frequency can be calculated as:
CCLK = 1 t
CCLK
3.1 2 5M H z
66 .7M H z
CLKIN
= f
XTAL
15). To determine switching frequencies for
to
@BOOT, CLKCFG[]->PLLM[]
RESET
INPUT
(PLLM/PLLD)
AMP
÷2
00 = 6
01 = 32
10 = 16
11 = RESERVED
0
1
I NDIV[8]
Figure 3. Core Clock and System Clock Relationship to CLKIN
+
–
Rev. B | Page 18 of 52 | June 2008
4096
FILTER
LOOP
PLLM[5..0]
DELAY
÷1
CLKOUTEN[12]
M
-
CLKIN
64
MULTIPLIER
BLOCK
VCO
1 6 0 M H z < VC O_ OU T < 8 0 0M H z
the serial ports, divide down the internal clock, using the pro-
grammable divider control of each port (DIVx for the
serial ports).
Figure 3
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency never
exceeds f
follows:
f
where:
PLLM = multiplier value programmed.
PLLD = divider value programmed.
f
f
f
VCO
INPUT
INPUT
INPUT
PLLD[7..6]
÷1, 2, 4, 8
= 2
= input frequency to the PLL.
= CLKIN when the input divider is disabled.
= CLKIN/2 when the input divider is enabled.
N
shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
vco
1
0
PLLM
DIVEN[9]
in
Table
1
BUFF
f
PLLBP[15]
INPUT
16. The VCO frequency is calculated as
0
1
SDRATIO[20..18]
÷2
CLKOUT
RSTO UT
CORERST
3, 3.5, 4
÷2, 2.5,
or
PCLK
(IOP)
1 00 M Hz
2 66 M Hz
CCLK
SDCLK
t o