ep2c35 Altera Corporation, ep2c35 Datasheet - Page 136

• Manufacturer Part Number: ep2c35
• Description: Cyclone Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Specifications
5–46
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
LVDS
RSDS
MINI_LVDS
PCI
PCI-X
Table 5–43. Cyclone II I/O Output Delay for Row Pins (Part 4 of 4)
I/O Standard
This is the default setting in the Quartus II software.
These numbers are for commercial devices.
These numbers are for automotive devices.
Table
5–43:
Strength
Drive
—
—
—
—
—
Maximum Input and Output Clock Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–44
specifies the maximum output clock toggle rates at default load.
Table 5–46
for non-default load.
To calculate the output toggle rate for a non-default load, use this
formula:
t
t
t
t
t
t
t
t
t
t
Parameter
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
The toggle rate for a non-default load
specifies the maximum input clock toggle rates.
specifies the derating factors for the output clock toggle rate
Industrial
motive
/Auto-
1216
1340
1216
1340
1216
1340
1113
1113
989
989
Fast Corner
Commer-
1275
1407
1275
1407
1275
1407
1036
1168
1036
1168
cial
Speed
Grade
2089
2297
2089
2297
2089
2297
2070
2278
2070
2278
–6
Speed
Grade
2184
2421
2184
2421
2184
2421
2214
2451
2214
2451
(2)
–7
Speed
Grade
2272
2545
2272
2545
2272
2545
2352
2625
2352
2625
(3)
–7
Altera Corporation
February 2008
Table 5–45
Speed
Grade
2278
2545
2278
2545
2278
2545
2358
2625
2358
2625
–8
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps