xc4000a Xilinx Corp., xc4000a Datasheet
xc4000a
Related parts for xc4000a
xc4000a Summary of contents
Page 1
... XC4000 devices for more random designs requiring additional routing resources. The equivalent devices are pin-compatible and are avail- able in identical packages, but they are not bitstream compatible. In order to move from a XC4000A to a XC4000, or vice versa, the design must be recompiled. XC4002A XC4003A ...
Page 2
... XC4000A Logic Cell Array Family Absolute Maximum Ratings Symbol Description V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering temperature ( 1/16 in. = 1.5 mm) SOL T Junction temperature J Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. ...
Page 3
Wide Decoder Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The ...
Page 4
... XC4000A Logic Cell Array Family Horizontal Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions ...
Page 5
Guaranteed Input and Output Parameters (Pin-to-Pin) All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this ...
Page 6
... XC4000A Logic Cell Array Family IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions ...
Page 7
CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The ...
Page 8
... XC4000A Logic Cell Array Family CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions ...
Page 9
CLB RAM Timing Characteristics ADDRESS WRITE WRITE ENABLE DATA IN READ X,Y OUTPUTS VALID READ, CLOCKING DATA INTO FLIP-FLOP CLOCK XQ,YQ OUTPUTS READ DURING WRITE WRITE ENABLE DATA IN (stable during WE) X,Y OUTPUTS DATA IN (changing during WE) X,Y ...
Page 10
... XC4000A Logic Cell Array Family 2-80 ...
Page 11
Pin Bound Description PC 84 PQ100 VQ100 PG120 Scan VCC – I/O (A8 I/O (A9 – – – ...
Page 12
... XC4000A Logic Cell Array Family Pin Description PC84 VQ100 PQ100 PG120 VCC 2 89 I/O (A8 I/O (A9 I/O – 92 I/O – 93 I/O (A10 I/O (A11 – – – I/O (A12 I/O (A13 – – – – – – I/O (A14 SGCK1 (A15,I/ VCC ...
Page 13
Pin Bound Description PC84 TQ144 PQ160 PG120 Scan VCC 2 128 142 G3 I/O (A8) 3 129 143 G1 I/O (A9) 4 130 144 F1 I/O – 131 145 E1 I/O – 132 146 F2 I/O (A10) 5 133 147 ...
Page 14
... XC4000A Logic Cell Array Family Pin Description PC84 TQ144 PQ160 PQ208 PG156 VCC 2 128 142 I/O (A8) 3 129 143 I/O (A9) 4 130 144 I/O – 131 145 I/O – 132 146 – – – – – – – – I/O (A10) 5 133 147 I/O (A11) 6 134 148 I/O – ...
Page 15
XC4005A Pinouts (continued) Pin Descriptions PC84 TQ144 I/O – 80 – – – – – – – – – – – – GND – 81 I/O – 82 I/O – 83 I/O (D5 I/O (CS0 – ...
Page 16
... XC4000A Logic Cell Array Family For a detailed description of the device architecture, see pages 2-9 through 2-31. For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55. For detailed lists of package pinouts, see pages 2-57 through 2-81 through 2-85. For package physical dimensions and thermal data, see Section 4. ...