xc4000h Xilinx Corp., xc4000h Datasheet - Page 23
xc4000h
Manufacturer Part Number
xc4000h
Description
Logic Cell Array Families
Manufacturer
Xilinx Corp.
Datasheet
1.XC4000H.pdf
(40 pages)
- Current page: 23 of 40
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Figure 21. Start-up Timing
XC2000
XC3000
XC4000
CCLK_NOSYNC
XC4000
CCLK_SYNC
XC4000
UCLK_NOSYNC
XC4000
UCLK_SYNC
Note: Thick lines are default option.
CCLK
Synchronization
Uncertainty
Global Reset
Global Reset
DONE
I/O
DONE
I/O
DONE
I/O
DONE
I/O
DONE
I/O
DONE
I/O
GSR Active
GSR Active
GSR Active
GSR Active
Length Count Match
C1, C2 or C3
DONE IN
C1
C1
C1
Di
Di
DONE IN
Di+1
Di+1
C2
C2
C2
F
U2
U2
U2
U2
Di
2-29
UCLK Period
Di
Di+1
Di+1
U3
U3
U3
F
C3
C3
C3
CCLK Period
Di+2
Di+2
U4
U4
U4
F
F
F
C4
C4
C4
F
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
X3459
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