xa3s100e Xilinx Corp., xa3s100e Datasheet - Page 33

• Manufacturer Part Number: xa3s100e
• Description: Xa Spartan-3e Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Serial Peripheral Interface Configuration Timing
Table 41: Timing for SPI Configuration Mode
Table 42: Configuration Timing Requirements for Attached SPI Serial Flash
DS635 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
T
T
T
T
f
C
Symbol
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
CCS
DSU
DH
V
Symbol
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
Description
Description
www.xilinx.com
T
T
T
Minimum
CCS
V
DSU
f
T
≤
C
50
0
DH
≥
≤
Requirement
≤
T
----------------------------- -
T
MCCLn
≤
T
T
CCLKn min
MCCL1
(see
(see
MCCL1
See
See
See
T
MCCH1
1
Maximum
Table
Table
Table 39
Table 39
Table 39
–
(
T
–
–
-
-
DCC
T
)
T
35)
35)
CCO
CCO
Units
Units
MHz
ns
ns
ns
ns
ns
ns
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