xc6vlx760 Xilinx Corp., xc6vlx760 Datasheet - Page 7

• Manufacturer Part Number: xc6vlx760
• Description: Fpga
• Manufacturer: Xilinx Corp.

The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are
made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test
access port (TAP).
Low-Power Gigabit Transceiver
Ultra-fast serial data transmission between ICs, over the backplane, or over longer distances is becoming increasingly
popular and important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the
signal integrity issues at these high data rates.
All but one Virtex-6 device has between 8 to 36 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter
and receiver capable of operating at a data rate between 155 Mb/s and 6.5 Gb/s. The transmitter and receiver are
independent circuits that use separate PLLs to multiply the reference frequency input by certain programmable numbers
between 2 and 25, to become the bit-serial data clock. Each GTX transceiver has a large number of user-definable features
and parameters. All of these can be defined during device configuration, and many can also be modified during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, 20, 32, or 40. The
transmitter output drives the PC board with a single-channel differential current-mode logic (CML) output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B,
64B/66B, or the 64B/67B algorithm to guarantee a sufficient number of transitions. The bit-serial output signal drives two
package pins with complementary CML signals. This output signal pair has programmable signal swing as well as
programmable pre-emphasis to compensate for PC board losses and other interconnect characteristics.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel
stream of words, each 8, 10, 16, 20, 32, or 40 bits wide. The receiver takes the incoming differential data stream, feeds it
through a programmable equalizer (to compensate for PC board and other interconnect characteristics), and uses the F
input to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ)
encoding and optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then
transferred into the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio can be 8, 10, 16, 20, 32,
or 40.
Out-of-Band Signaling
The GTX transceivers provide Out-of-Band (OOB) signaling, often used to send low-speed signals from the transmitter to
the receiver, while high-speed serial data transmission is not active, typically when the link is in a power-down state or has
not been initialized.
Integrated Interface Blocks for PCI Express Designs
The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission
uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.
The PCI Express Base Specification Revision 2.0 is backwards compatible with Revision 1.1 and defines a configurable raw
data rate of 2.5 Gb/s, or 5.0 Gb/s per lane in each direction. To scale bandwidth, the specification allows multiple lanes to be
joined to form a larger link between PCI Express devices.
All Virtex-6 LXT and SXT devices include an integrated interface block for PCI Express that can be configured as an
Endpoint or Root Port, designed to the PCI Express Base Specification Revision 2.0. The Root Port can be used:
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This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s data rate
or 1, 2, and 4 lanes at the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block
offer a flexible maximum payload size of up to 1024 bytes. The integrated block interfaces to the GTX transceivers for serial
DS150 (v1.0) February 2, 2009
Advance Product Specification
To build the basis for a compatible Root Complex
To allow custom FPGA-FPGA communication via the PCI Express protocol
To attach ASSP Endpoint devices such as Fibre-channel HBAs to the FPGA
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Virtex-6 Family Overview
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