ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 207
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
Flash Control Register
The Flash Control register enables or disables memory access to Flash. I/O access to the
Flash control registers and I/O programming to Flash memory are still possible while
Flash memory space access is disabled.
The minimum access time of the internal Flash is 60 ns. The Flash control register must be
configured to provide the appropriate number of WAIT states based on the system clock
frequency of the eZ80F92 device. Default on RESET is for 4 WAIT states to be inserted
for Flash memory access.
Table 116. Flash Control Register; (FLASH_CTRL= 00F8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7:5]
FLASH_WAIT
[4]
[3]
FLASH_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
0
1
000
R/W
0 Wait states are inserted when Flash is active.
1 Wait state is inserted when Flash is active.
2 Wait states are inserted when Flash is active.
3 Wait states are inserted when Flash is active.
4 Wait states are inserted when Flash is active.
5 Wait states are inserted when Flash is active.
6 Wait states are inserted when Flash is active.
7 Wait states are inserted when Flash is active.
Reserved.
Flash Memory Access is disabled.
Flash Memory Access is enabled.
Reserved.
7
1
R/W
6
0
R/W
5
0
R
4
0
R/W
3
1
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
Flash Memory
R
0
0
200
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