ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 62
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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eZ80F92/eZ80F93
Product Specification
55
T1
T2
T
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
®
Figure 10. Example: Z80
Bus Mode Write Timing
Intel
Bus Mode
TM
Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four-
state memory transfer similar to that found on Intel-style microcontrollers. The bus signals
and eZ80F92 device pins are mapped as displayed in
Figure 11
on page 56. In Intel bus
mode, you can select either multiplexed or nonmultiplexed address and data buses. In non-
multiplexed operation, the address and data buses are separate. In multiplexed operation,
the lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], dur-
ing State T1 of the Intel bus mode cycle. During multiplexed operation, the lower byte of
the address bus also appears on the address bus in addition to the data bus.
PS015313-0508
Chip Selects and Wait States
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