ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 55

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Chip Selects and Wait States
PS015313-0508
Memory and I/O Chip Selects
Memory Chip Select Operation
The eZ80F92 device generates four Chip Selects for external devices. Each Chip Select
may be programmed to access either memory space or I/O space. The Memory Chip
Selects can be individually programmed on a 64 KB boundary. The I/O Chip Selects can
each choose a 256-byte section of I/O space. In addition, each Chip Select may be
programmed for up to 7 wait states.
Each of the Chip Selects can be enabled for either the memory address space or the
I/O address space, but not both. To select the memory address space for a particular Chip
Select, CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a
particular Chip Select, CSX_IO must be set to 1. After RESET, the default is for all Chip
Selects to be configured for the memory address space. For either the memory address
space or the I/O address space, the individual Chip Selects must be enabled by setting
CSx_EN (CSx_CTL[3]) to 1.
Operation of each of the Memory Chip Selects is controlled by three control registers.
To enable a particular Memory Chip Select, the following conditions must be met:
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•
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If all of the foregoing conditions are met to generate a Memory Chip Select, then the
following actions occur:
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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular Chip Select is valid for a single 64 KB page.
The Chip Select is enabled by setting CSx_EN to 1
The Chip Select is configured for Memory by clearing CSX_IO to 0
The address is in the associated Chip Select range:
No higher priority (lower number) Chip Select meets the above conditions
A memory access instruction must be executing
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low)
MREQ is asserted (driven Low)
Depending upon the instruction, either RD or WR is asserted (driven Low)
CSx_LBR[7:0]
≤
ADDR[23:16]
≤
CSx_UBR[7:0]
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
48