ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 41

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS013014-0107
Clock Peripheral Power-Down Registers
The eZ80 CPU can be brought out of HALT mode by any of the following operations:
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To minimize current in HALT mode, the system clock must be disabled for all unused on-
chip peripherals through the Clock Peripheral Power-Down Registers.
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See
Non-maskable interrupt (NMI).
Maskable interrupt.
RESET through the external RESET pin driven Low.
Watchdog Timer time-out (if configured to generate either an NMI or RESET upon
time-out).
RESET through execution of a Debug RESET command.
Table 4
and
Table
5.
Product Specification
Low-Power Modes
35