ez80l92 ZiLOG Semiconductor, ez80l92 Datasheet - Page 81

• Manufacturer Part Number: ez80l92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS013014-0107
Watchdog Timer Registers
determine the source of the NMI event, provided that the last RESET was not caused by
the WDT.
Watchdog Timer Control Register
The Watchdog Timer Control register, described in
ter used to enable the Watchdog Timer, set the time-out period, indicate the source of the
most recent RESET, and select the required operation upon WDT time-out.
Table 27. Watchdog Timer Control Register (WDT_CTL = 0093h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG
[4:3]
WDT_CLK
2
RESERVED
Note: *RST_FLAG is only cleared by a non-WDT RESET.
*
Value
00
01
10
11
0
1
0
1
0
1
0
R/W
7
0
Description
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be
disabled without a full RESET.
WDT time-out resets the CPU.
WDT time-out generates a nonmaskable interrupt (NMI) to
the CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 kHz
on-chip oscillator or 50/60Hz input as set by RTC_CTRL[4]) .
Reserved.
Reserved.
Reserved.
R/W
6
0
0/1
R
5
R/W
Table
4
0
27, is an 8-bit Read/Write regis-
R/W
3
0
Product Specification
R
2
0
eZ80L92 MCU
Watchdog Timer
R/W
1
0
R/W
0
0
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