mm908e622 Freescale Semiconductor, Inc, mm908e622 Datasheet - Page 48

• Manufacturer Part Number: mm908e622
• Description: Mm908e622 Integrated Quad Half-bridge, Triple High-side And Ec Glass Driver With Embedded Mcu And Lin For High End Mirror
• Manufacturer: Freescale Semiconductor, Inc

908E622 SERIAL PHERIPHERAL INTERFACE (SPI)
communication link between the MCU and the analog die.
Master Address Byte
A4 - A0
48
908E622
SPSCK
Functional Device Operation
Logic Commands and Registers
MOSI
MISO
The Serial Peripheral Interface (SPI) creates the
The interface consists of four terminals
• MOSI - Master Out Slave In (internal pull-down)
• MISO - Master In Slave Out
• SPSCK - Serial Clock (internal pull-down)
• SS - Slave Select (internal pull-up)
• During the inactive phase of SS, the new data transfer
• The MOSI, MISO will change data on a rising edge of
• The MOSI, MISO will be sampled on a falling edge of
• The data transfer is only valid, if exactly 16 sample clock
• After a write operation the transmitted data will be
• Register read data is internally latched into the SPI, at
• SS high will force MISO to high impedance
include the address of the desired register.
SS
will be prepared. The falling edge on the SS line,
indicates the start of a new data transfer (framing) and
puts MISO in the low impedance mode. The first valid
data are moved to MISO with the rising edge of SPSCK.
SPSCK.
SPSCK.
edges are present in the active phase of SS.
latched into the register, by the rising edge of SS.
the time when the parity bit is transferred
Rising edge of SPSCK
Change MISO/MOSI
Output
R/W
S7
Falling edge of SPSCK
Sample MISO/MOSI
Input
A4
S6
Read/Write, Address, Parity
A3
S5
System Status Register
A2
S4
LOGIC COMMANDS AND REGISTERS
A1
S3
A0
S2
Figure 31. SPI Protocol
Slave latch
register address
S1
P
S0
X
The master sends address and data, the slave returns
system status and the data of the selected address.
R/W
Parity P
even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.
and ignored for read operations.
Bit X
A complete data transfer via the SPI, consists of 2 bytes.
includes the information if it is a read or a write operation.
• If R/W = 1 (read operation), second byte of master
• If R/W = 0 (write operation), master sends data to be
completes the total number of 1 bits of (R/W,A[4-0]) to an
The parity bit is only evaluated during a write operations
not used
contains no valid information, slave just transmits back
register data.
written in the second byte, slave sends concurrently
contents of selected register prior to write operation,
write data is latched in the SmartMOS registers on
rising edge of SS
D7
D7
D6
D6
D5
D5
Analog Integrated Circuit Device Data
Data (Register write)
Data (Register read)
D4
D4
D3
D3
Freescale Semiconductor
D2
D2
D1
D1
D0
D0
Slave latch
data