ade7566 Analog Devices, Inc., ade7566 Datasheet
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ade7566 Summary of contents
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... ADE core reduces the program memory size requirement, making it easy to integrate complicated design into flash memory. The ADE7566/ADE7569 also include a 108-segment LCD driver. This driver generates voltages capable of driving LCDs One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781 ...
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... ADE7566/ADE7569 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Energy Metering ........................................................................... 5 Analog Peripherals ....................................................................... 6 Digital Interface ............................................................................ 7 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution................................................................................ 14 Pin Configuration and Function Descriptions........................... 15 Typical Performance Characteristics ........................................... 17 Terminology ...
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... Read and Write Operations .....................................................126 Receive and Transmit FIFOs.............................................127 Dual Data Pointers........................................................................128 I/O Ports .........................................................................................129 Parallel I/O.................................................................................129 I/O Registers ..............................................................................130 Port 0...........................................................................................133 Port 1...........................................................................................133 Port 2...........................................................................................133 Determining the Version of the ADE7566/ADE7569..............134 Outline Dimensions......................................................................135 Ordering Guide .........................................................................136 Rev Page 3 of 136 ADE7566/ADE7569 ...
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... VDCIN ADC POR UART TIMER LDO LDO Figure 1. Functional Block Diagram Rev Page 4 of 136 P2.0 (FP18) 12 P2.1 (FP17) 13 ADE7566/ADE7569 P2.2 (FP16) 14 P2.3 (SDEN) 44 LCDVP1 19 LCDVP2 16 LCDVA 18 3V/5V LCD LCDVB 17 CHARGE PUMP LCDVC 15 COM0 4 ... COM3 1 108-SEGMENT LCD DRIVER FP0 35 ...
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... Rev Page 5 of 136 ADE7566/ADE7569 −40°C to +85°C, unless otherwise noted. MIN MAX Test Conditions/Comments Phase lead 37° Phase lag 60° Over a dynamic range of 1000 25° 3 100 mV rms/120 ±100 mV rms ...
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... ADE7566/ADE7569 ANALOG PERIPHERALS Table 3. Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, V Power Supply Operating Range 1 No Missing Codes 2 Conversion Delay PSM0 V Gain DCIN V Gain BAT Temperature Gain V Code DCIN V Code at 3.7 V BAT Temperature Code at 25°C PSM1, PSM2 V Gain DCIN V Gain BAT ...
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... MHz Crystal = 32.768 kHz and CD[2: kHz Crystal = 32.768 kHz and CD[2:0] = 0b111 Rev Page 7 of 136 ADE7566/ADE7569 Unit Test Conditions/Comments 1/3 bias modes V 1/3 bias mode V Current on segment line = −2 μA V Current on segment line = −2 μA V Current on segment line = − ...
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... ADE7566/ADE7569 Parameter LOGIC OUTPUTS Output High Voltage SOURCE 3 Output Low Voltage SINK 4 START-UP TIME PSM0 Power-On Time From Power Saving Mode 1 (PSM1) PSM1 → PSM0 From Power Saving Mode 2 (PSM2) PSM2 → PSM1 PSM2 → PSM0 POWER SUPPLY INPUTS ...
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... The ADE7566/ADE7569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR. ...
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... ADE7566/ADE7569 Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge DSU t Data input hold time after SCLK edge ...
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... MHz. CORE DAV BITS [6:1] MSB MSB IN BITS [6:1] t DHD Figure 5. SPI Master Mode Timing (SPICPHA = 0) Rev Page 11 of 136 ADE7566/ADE7569 Min Typ Max SPIR × t (SPIR + 1) × t CORE CORE SPIR × t (SPIR + 1) × t CORE CORE 3 × ...
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... ADE7566/ADE7569 Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge DSU t Data input hold time after SCLK edge ...
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... CORE DAV MSB BITS [6:1] MSB IN BITS [6: DSU DHD Figure 7. SPI Slave Mode Timing (SPICPHA = 0) Rev Page 13 of 136 ADE7566/ADE7569 Min Typ Max 145 1 6 × t CORE 1 6 × t CORE × 0.5 μs CORE ...
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... ADE7566/ADE7569 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 11. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND and Digital Input Voltage to DGND Digital Output Voltage to DGND ...
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... Scale Figure 8. Pin Configuration 2 C-Compatible, or Data Out for SPI Port apparent power information. rms Rev Page 15 of 136 ADE7566/ADE7569 INT0 48 XTAL1 47 XTAL2 46 45 BCTRL/INT1/P0.0 SDEN/P2 P0.2/CF1/RTCCAL 42 P0.3/CF2 P0.4/MOSI/SDATA 41 P0 ...
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... V 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the SWOUT ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to INTD this pin. This pin should be decoupled with a 10 μ ...
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... Figure 13. Current RMS Error as a Percentage of Reading (Gain = 1) over –0.5 –1.0 –1.5 –2.0 10 100 Figure 14. Current RMS Error as a Percentage of Reading (Gain = 1) over Rev Page 17 of 136 ADE7566/ADE7569 2.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 1.5 1.0 +85° 0.866 +25° 0.866 0.5 –40° 0.866 0 +85° ...
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... ADE7566/ADE7569 0.5 GAIN = 1 INTEGRATOR OFF 0.4 INTERNAL REFERENCE 0.3 0 3.3V rms I ; 3.3V rms 0 3.43V rms 0 –0 3.13V rms –0.2 –0.3 –0.4 –0.5 0.1 1 CURRENT CHANNEL (% of Full Scale) Figure 15. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1) over Power Supply with Internal Reference 1.0 GAIN = 1 INTEGRATOR OFF 0.8 INTERNAL REFERENCE ...
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... Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = 16) over 10 100 Figure 25. Current RMS Error as a Percentage of Reading (Gain = 16) over 10 100 Figure 26. Current RMS Error as a Percentage of Reading (Gain = 16) over Rev Page 19 of 136 ADE7566/ADE7569 1.0 GAIN = 16 INTEGRATOR OFF 0.8 INTERNAL REFERENCE 0.6 –40° +85° ...
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... ADE7566/ADE7569 2.0 GAIN = 16 MID CLASS C INTEGRATOR ON 1.5 INTERNAL REFERENCE 1.0 –40° +85° 0.5 +25° 0.5 0.5 –40° 0.5 0 +25° +85° –0.5 –1.0 –1.5 MID CLASS C –2.0 0.1 1 CURRENT CHANNEL (% of Full Scale) Figure 27. Active Energy Error as a Percentage of Reading (Gain = 16) over Power Factor with Internal Reference, Integrator On 1 ...
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... With the digital integrator on, the phase is corrected to within ±0.4° over a range Hz. Power Supply Rejection (PSR) This quantifies the ADE7566/ADE7569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3 taken ...
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... ADE7566/ADE7569 SFR MAPPING Table 14. Mnemonic Address INTPR 0xFF SCRATCH4 0xFE SCRATCH3 0xFD SCRATCH2 0xFC SCRATCH1 0xFB BATVTH 0xFA STRBPER 0xF9 IPSMF 0xF8 TEMPCAL 0xF7 RTCCOMP 0xF6 BATPR 0xF5 PERIPH 0xF4 DIFFPROG 0xF3 B 0xF0 VDCINADC 0xEF LCDSEGE2 0xED IPSME 0xEC SPISTAT 0xEA ...
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... POWER MANAGEMENT The ADE7566/ADE7569 have elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 15). Table 15. Power Management SFRs SFR Address R/W Mnemonic ...
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... ADE7566/ADE7569 Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8) Bit No. Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC RESERVED 0 3 0xFB FVADC 0 2 0xFA FBAT 0 1 0xF9 FBSO 0 0 0xF8 FVDCIN 0 Table 18. Battery Switchover Configuration SFR (BATPR, 0xF5) Bit No ...
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... Set this bit to shut down the core and enter PSM2 if in the PSM1 operating mode. Reserved. Controls the core clock frequency CORE CD[2:0] Result (f in MHz) CORE 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 111 0.032 Rev Page 25 of 136 ADE7566/ADE7569 = 4.096 MHz CORE ...
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... Battery Switchover BAT DD section input pin that can be connected DCIN 3 signal. This input is intended for power supply super- visory purposes and does not provide power to the ADE7566/ ADE7569 circuitry (see the Battery Switchover section DCIN ...
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... IPSMF flag register. FPSM EPSM RESERVED ESAG RESERVED EVADC FPSM FSAG RESERVED FVADC PTI RESERVED PSI EADE Figure 31. PSM Interrupt Sources Rev Page 27 of 136 ADE7566/ADE7569 PENDING PSM TRUE? INTERRUPT EBAT EBSO EVDCIN FBAT FBSO FVDCIN ETI EPSM ESI ...
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... SW BAT V ADC PSM Interrupt DCIN The ADE7566/ADE7569 can be configured to generate a PSM interrupt when V changes magnitude by more than a config- DCIN urable threshold. This threshold is set in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), which is described in Table 48. See the External Voltage Measurement section for more information ...
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... voltage regulator IC. The preregulated dc voltage, typically can be connected to V resistor divider. A 3.6 V battery can be connected to V Figure 32 shows how the ADE7566/ADE7569 power supply inputs are set up in this application. Figure 33 shows the sequence of events that occur if the main power supply generated by the PSU started to fail in the power meter application shown in Figure 32 ...
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... ADE7566/ADE7569 Table 26. Power Supply Event Timing Operating Modes Parameter Time Description min Time between when min Time between when Time between when V 3 switchover. t 130 ms Time between when power supply restore conditions are met (V 4 BATPR[1:0] = 0b01 – ...
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... The ADE7566/ADE7569 remain in PSM2 until power supply occurs DD an event occurs to wake it up. In PSM2, the ADE7566/ADE7569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 when entering PSM2 (see Table 20 to Table 24). ...
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... ADE7566/ADE7569 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7566/ADE7569 from PSM2. The events that can cause the ADE7566/ADE7569 to wake up from PSM2 are listed in the wake-up events column in Table 28. The interrupt flag associated with these events must be cleared prior to executing instructions that put the ADE7566/ADE7569 in PSM2 mode after wake-up. ...
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... Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section). Servicing Wake-Up Events (PSM2 to PSM1) The ADE7566/ADE7569 may need to wake up from PSM2 to service wake-up events (see the 3.3 V Peripherals and Wake-Up Events section). PSM1 code execution begins at the power-on reset vector ...
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... ADE7566/ADE7569 ENERGY MEASUREMENT The ADE7566/ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFR registers for the majority of energy measurements ...
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... INTEGRATOR WGAIN[11:0] MULTIPLIER dt LPF2 WATTOS[15:0] π VARGAIN[11:0] 2 Ф LPF2 VAROS[15:0] IRMSOS[11:0] VAGAIN[11:0] × 2 LPF VRMSOS[11:0] × 2 VADIV[7:0] LPF HPF Figure 37. Energy Metering Block Diagram Rev Page 35 of 136 ADE7566/ADE7569 CF1NUM[15:0] DFC CF1DEN[15:0] CF2NUM[15:0] DFC VARDIV[7:0] CF2DEN[15: WDIV[7:0] METERING SFRs CF1 CF2 ...
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... ADE7566/ADE7569 ENERGY MEASUREMENT REGISTERS Table 31. Energy Measurement Register List Address Length MADDPT[6:0] (Bits) Mnemonic R/W 0x00 Reserved 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR R 24 0x04 VARHR 0x05 RVARHR 0x06 LVARHR R 24 0x07 VAHR R 24 0x08 RVAHR R 24 ...
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... CF2NUM R/W 16 0x2A CF2DEN R/W 16 0x3B Reserved 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved 1 This function is not available in the ADE7566 part. ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS Table 32. MODE1 Register (0x0B) Bit No. Mnemonic Default 7 SWRST 0 6 DISZXLPF 0 5 INTE 0 4 SWAPBITS 0 3 PWRDN ...
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... IRMSNOLOAD VANOLOAD[1: VARNOLOAD[1: APNOLOAD[1: This function is not available in the ADE7566 part. Description Waveform 2 Selection for Samples Mode. WAV2SEL[2:0] Source 000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output 100 ...
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... Logic 1 enables positive only accumulation of active power in energy register and pulse output. 0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output. 1 This function is not available in the ADE7566 part. Table 37. GAIN Register (0x1B) Bit No. Mnemonic Default Description ...
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... When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core. 0 AEHF When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core. 1 This function is not available in the ADE7566 part. Rev Page 40 of 136 ...
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... When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core. ANALOG INPUTS Each ADE7566/ADE7569 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V /V and ± ...
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... The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7566/ ADE7569 is 4.096 MHz/5 (819.2 kHz), and the band of interest ANALOG ...
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... Figure 42. ADC and Signal Processing in Current Channel Outline Dimensions ADC Transfer Function Both ADCs in the ADE7566/ADE7569 are designed to produce the same output code for the same input signal level. With a full-scale signal on the input of 0.4 V and an internal reference of 1.2 V, the ADC output code is nominally 2,147,483 or 0x20C49B. ...
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... ADE7566/ADE7569 ×1, ×2, ×4, ×8, ×16 {GAIN[7:5 PGA2 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV 0V ANALOG INPUT RANGE *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED. ...
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... Antialiasing Filter section). When the digital integrator is switched off, the ADE7569 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt. Rev Page 45 of 136 ADE7566/ADE7569 ...
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... FLAG BIT Figure 51. Zero-Crossing Timeout Detection Period or Frequency Measurements The ADE7566/ADE7569 provide the period or frequency measurement of the line. The period or frequency measurement is selected by clearing or setting FREQSEL bit in the MODE2 register (0x0C). The period/frequency register, PER_FREQ Register (0x0A unsigned 16-bit register that is updated every period ...
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... SAG level register are greater. Peak Detection The ADE7566/ADE7569 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 53 illustrates the behavior of the peak detection for the voltage channel. Both voltage and current channels are monitored at the same time ...
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... The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7566/ADE7569 provide a means of digitally calibrating these small phase errors. The part allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors ...
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... Figure 56. Current Channel RMS Signal Processing with PGA1 = PGA1 = 16. The current rms measurement provided in the ADE7566/ADE7569 is accurate to within 0.5% for signal inputs between full scale and full scale/500. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant ...
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... V register. The voltage rms rms measurement provided in the ADE7566/ADE7569 is accurate to within ±0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a V/LSB constant. ...
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... Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB. Active Power Sign Detection The ADE7566/ADE7569 detect a change of sign in the active power. The APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to Bit APSIGN in the ACCMODE register (0x0F). ...
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... When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the active energy contents. When both bits are set, the ADE7566/ADE7569 are set the more restrictive mode, the positive only accumulation mode. When POAM in the ACCMODE register (0x0F) is set, only positive power contributes to the active energy accumulation ...
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... The watt gain register is used to carry out power calibration in the ADE7566/ADE7569. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, that is, 0x7FF. ...
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... INTERRUPT STATUS REGISTERS Figure 63. Energy Accumulation in Absolute Accumulation Mode Active Energy Pulse Output All of the ADE7566/ADE7569 circuitry has a pulse output whose frequency is proportional to active power (see the Active Power Calculation section). This pulse frequency output uses the calibrated signal from the WGAIN register output, and its behavior is consistent with the setting of the active energy accumulation mode in the ACCMODE register (0x0F) ...
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... REACTIVE POWER CALCULATION FOR THE ADE7569 Reactive power, a function available for the ADE7569, but not for the ADE7566, is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 20 gives an expression for the instanta- neous reactive power signal system when the phase of the current channel is shifted by 90° ...
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... The reactive energy register (VARHR[23:0]) represents the upper 24 bits of this internal register. The VARHR register and its function is available for the ADE7569, but not for the ADE7566. The discrete time sample period (T) for the accumulation register in the ADE7569 is 1.22 μs (5/MCLK). As well as calculating the ...
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... VARGAIN[11:0] REACTIVE POWER SIGNAL DIGITAL-TO-FREQUENCY CONVERTER 5 CLKIN WAVEFORM REGISTER VALUES TIME (nT) Figure 66. Reactive Energy Calculation Rev Page 57 of 136 ADE7566/ADE7569 UPPER 24 BITS ARE ACCESSIBLE THROUGH VARHR[23:0] REGISTER VARHR[23: OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL REACTIVE ENERGY ...
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... ADE7566/ADE7569 Integration Time Under Steady Load As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/ MCLK). With full-scale sinusoidal signals on the analog inputs and the VARGAIN and VARDIV registers set to 0x000, the integration time before the reactive energy register overflows is calculated in Equation 23 ...
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... The LSB size of these two registers is equivalent. TO DIGITAL-TO-FREQUENCY CONVERTER VARDIV[7:0] 23 LVARHR[23:0] ZERO-CROSSING CALIBRATION CONTROL DETECTION LINCYC[15:0] Figure 69. Line Cycle Reactive Energy Accumulation Mode Rev Page 59 of 136 ADE7566/ADE7569 0 ACCUMULATE REACTIVE ENERGY IN INTERNAL 0 REGISTER AND UPDATE THE LVARHR REGISTER AT THE END OF LINCYC HALF-LINE CYCLES ...
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... Figure 70 illustrates the signal processing for the calculation of the apparent power in the ADE7566/ADE7569. The apparent power signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 25 ...
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... Apparent Energy Apparent Power The ADE7566/ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time ...
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... AMPERE-HOUR ACCUMULATION In case of a tampering situation where no voltage is available to the energy meter, the ADE7566/ADE7569 is capable of accumu- lating the ampere-hour instead of apparent power into the VAHR, RVAHR, and LVAHR registers. When Bit 3 (VARMSCFCON) of the MODE2 register (0x0C) is set, the VAHR, RVAHR, LVAHR, ...
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... The two pulse output circuits have separate configuration bits in the MODE2 Register (0x0C. Setting the CFxSEL bits to 0b00, 0b01, or 0b1x configure the DFC to create a pulse output proportional to active power, to reactive power (not available in the ADE7566 apparent power or I The selection between I and apparent power is done by the rms VARMSCFCON bit in the MODE2 register (0x0C) ...
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... ADE7566/ADE7569 ENERGY MEASUREMENT INTERRUPTS The energy measurement part of the ADE7566/ADE7569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), Interrupt Enable 2 SFR (MIRQENM, 0xDA), and Interrupt Enable 3 SFR (MIRQENH, 0xDB) enable the energy measurement interrupts that are allowed to interrupt the 8052 core ...
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... TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. These measure- ments enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it does not drift ...
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... ADE7566/ADE7569 Table 48. Temperature and Supply Delta SFR (DIFFPROG, 0xF3) Bit No. Mnemonic Default Reserved TEMP_DIFF[2: VDCIN_DIFF[2:0] 0 Table 49. Start ADC Measurement SFR (ADCGO, 0xD8) Bit No. Address Mnemonic 7 0xDF PLLACK 0xDE to 0xDB Reserved 2 0xDA VDCIN_ADC_GO 1 0xD9 TEMP_ADC_GO 0 0xD8 BATT_ADC_GO Table 50 ...
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... Temperature ADC Value SFR (TEMPADC, 0xD7). Note that there is no flag associated with this interrupt. BATTERY MEASUREMENT To provide a digital battery measurement, each ADE7566/ ADE7569 includes a dedicated ADC. The battery measurement is available in an 8-bit SFR, the Battery ADC Value SFR (BATADC, 0xDF). The battery measurement has a resolution of 14 ...
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... Power Management Interrupt Flag SFR (IPSMF, 0xF8). EXTERNAL VOLTAGE MEASUREMENT The ADE7566/ADE7569 include a dedicated ADC to provide a digital measurement of an external voltage on the V 8-bit SFR, the VDCIN ADC Value SFR (VDCINADC, 0xEF), holds the results of the conversion. The resolution of the external voltage measurement is 15 ...
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... External Voltage ADC in PSM1 and PSM2 An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7566/ADE7569. • In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. • ...
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... ADE7566/ADE7569 8052 MCU CORE ARCHITECTURE The ADE7566/ADE7569 have an 8052 MCU core and use the 8052 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its enhancements used in the ADE7566/ADE7569. ...
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... Extended Port Configuration SFR (EPCFG, 0x9F). Result Enables MOVX instruction to use 256 bytes of extended RAM. Disables MOVX instruction. Rev Page 71 of 136 ADE7566/ADE7569 Description Contain 2-byte address of the data pointer. DPTR is the combination of DPH and DPL SFRs. Description Contain the 8 LSBs of the pointer for the stack. ...
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... The DPTR can be manipulated as a 16-bit register (DPTR = DPH, DPL two independent 8-bit registers (DPH, DPL). See Table 57 and Table 58. The ADE7566/ADE7569 support dual data pointers. See the Dual Data Pointers section. Stack Pointer (SP) The stack pointer keeps track of the current address at the top of the stack ...
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... Due to the limited number of I/O pins, the ADE7566/ADE7569 do not allow access to external code and data spaces. The ADE7566/ADE7569 provide 20 pins that can be used for general-purpose I/O. These pins are mapped to Port 0, Port 1, and Port 2. They are accessed through three bit-addressable 8052 SFRs, P0, P1, and P2. Another enhanced feature of the ...
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... Boolean and program branching instructions. These SFRs are labeled as bit-addressable and the bit addresses are given in the SFR Mapping section. Extended Internal RAM (XRAM) The ADE7566/ADE7569 provide 256 bytes of extended on-chip ONLY RAM. No external RAM is supported. This RAM is located in Address 0x0000 through Address 0x00FF in the extended RAM space ...
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... Extended Direct Addressing The DPTR register (see Table 59) is used to access internal extended RAM in extended indirect addressing mode. The ADE7566/ADE7569 have 256 bytes of XRAM, accessed through MOVX instructions. External memory spaces are not supported on this device. In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM ...
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... ADE7566/ADE7569 INSTRUCTION SET Table 63 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Table 63. Instruction Set Mnemonic Description ARITHMETIC ADD A,Rn Add Register to A. ADD A,@Ri Add Indirect Memory to A. ...
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... RET Return from Subroutine. RETI Return from Interrupt. ACALL addr11 Absolute Jump to Subroutine. AJMP addr11 Absolute Jump Unconditional. SJMP rel Short Jump (Relative Address). JC rel Jump on Carry Equal to 1. Rev Page 77 of 136 ADE7566/ADE7569 Bytes Cycles ...
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... ADE7566/ADE7569 Mnemonic Description JNC rel Jump on Carry Equal rel Jump on Accumulator = 0. JNZ rel Jump on Accumulator Not Equal to 0. DJNZ Rn,rel Decrement Register, JNZ Relative. LJMP Long Jump Unconditional. LCALL addr16 Long Jump to Subroutine. JB bit,rel Jump on Direct Bit = 1. JNB bit,rel Jump on Direct Bit = 0. ...
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... If the values are equal, program execution continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction. Affected Status Flag C Set if the source value is greater than the destination value. Cleared otherwise. Rev Page 79 of 136 ADE7566/ADE7569 ...
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... See the 3.3 V Peripherals and Wake-Up Events section to learn more about events that can wake the 8052 core from PSM2. The ADE7566/ADE7569 provide 12 interrupt sources with three priority levels. The power management interrupt is at the highest priority level. The other two priority levels are configurable through the Interrupt Priority SFR (IP, 0xB8) and Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) ...
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... Description Power Supply Monitor Interrupt. RTC Interval Timer Interrupt. ADE Energy Measurement Interrupt. Watchdog Timer Overflow Interrupt. Temperature ADC Interrupt. External Interrupt 0. Timer/Counter 0 Interrupt. External Interrupt 1. Timer/Counter 1 Interrupt. 2 SPI/I C Interrupt. UART Serial Port Interrupt. Timer/Counter 2 Interrupt. Rev Page 81 of 136 ADE7566/ADE7569 ...
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... A functional block diagram of the interrupt system is shown in Figure 83. Note that the PSM interrupt is the only interrupt in the highest priority level external wake-up event occurs to wake the ADE7566/ ADE7569 from PSM2, a pending external interrupt is generated. When the EX0 or EX1 bits in the Interrupt Enable SFR (IE, 0xA8) are set to enable external interrupts, the program counter is loaded with the IE0 or IE1 interrupt vector ...
Page 83
... RESET MIRQSTL.7 IN OUT LATCH RESET PSM2 IE0 PSM2 IE1 IN OUT LATCH RESET INDIVIDUAL INTERRUPT ENABLE GLOBAL INTERRUPT ENABLE (EA) Figure 83. Interrupt System Functional Block Diagram Rev Page 83 of 136 ADE7566/ADE7569 PRIORITY LEVEL LOW HIGH HIGHEST INTERRUPT POLLING SEQUENCE LEGEND AUTOMATIC CLEAR SIGNAL ...
Page 84
... ADE7566/ADE7569 INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by a RETI instruction. This allows program execution to resume from where it was interrupted ...
Page 85
... WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of 2 sec and creates a system reset if not cleared within 2 sec. The watchdog function can be disabled by clearing the watchdog enable bit (WDE) in the Watchdog Timer SFR (WDCON, 0xC0) ...
Page 86
... ADE7566/ADE7569 Writing to the Watchdog Timer SFR (WDCON, 0xC0) Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR. Disable Watch dog CLR EA SETB WDWR CLR WDE SETB EA This sequence is necessary to protect the WDCON SFR from code execution upsets that may unintentionally modify this SFR ...
Page 87
... LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without comprising any ADE7566/ADE7569 functions capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support LCDs ...
Page 88
... ADE7566/ADE7569 Table 77. LCD Configuration X SFR (LCDCONX, 0x9C) Bit No. Mnemonic Default 7 Reserved 0 6 EXTRES BIASLVL[5:0] 0 Table 78. LCD Bias Voltage When Contrast Control Is Enabled BIASLVL[ BLVL 4:0 × V REF ⎛ BLVL × + ⎜ REF ⎝ 31 Table 79. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit No ...
Page 89
... FP22 Function Select Bit General-Purpose I/ LCD Function. FP21 Function Select Bit General-Purpose I/ LCD Function. FP20 Function Select Bit General-Purpose I/ LCD Function. These bits should be left at 0 for proper operation. Rev Page 89 of 136 ADE7566/ADE7569 4× Multiplexing Frame Rate (Hz) f (Hz) Frame Rate (Hz) ...
Page 90
... ADE7566/ADE7569 Table 84. LCD Pointer SFR (LCDPTR, 0xAC) Bit No. Mnemonic Default Description 7 R/W 0 Read or Write LCD Bit. If this bit is set (1), the data in LCDDAT is written to the address indicated by the LCDPTR[5:0] bits. 6 RESERVED 0 Reserved ADDRESS 0 LCD Memory Address (see Table 87). Table 85. LCD Data SFR (LCDDAT, 0xAE) Bit No ...
Page 91
... FP7 FP5 FP5 FP5 FP3 FP3 FP3 FP1 FP1 FP1 Rev Page 91 of 136 ADE7566/ADE7569 LCDCONY,#01h ;start updating the data LCDDATA,#FFh LCDPTR,#80h OR 05h LCDCONY,#0FEh ;update finished LCDPTR,#07h R1, LCDDATA LCD Pointer SFR (LCDDAT, 0xAE) COM3 COM2 COM1 ...
Page 92
... The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE7566/ADE7569. There is also an option to use an external resistor ladder with a 3.3 V LCD. The EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) selects the resistor ladder or charge pump option ...
Page 93
... Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). To determine contrast setting for this 5 V LCD, Table 78 shows the BIASLVL[5:0] setting that corresponds 1/3 bias mode. The maximal bias level setting for this LCD is BIASLVL[5:0] = [101110]. =2048Hz LCDCLK Rev Page 93 of 136 ADE7566/ADE7569 ...
Page 94
... Flash/EE Memory Reliability The flash memory arrays on the ADE7566/ADE7569 are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. ...
Page 95
... FLASH MEMORY ORGANIZATION The flash memory provided by the ADE7566/ADE7569 are segmented into 32 pages of 512 bytes each the user to decide which flash memory to allocate for data memory recommended that each page be dedicated solely to program memory or data memory. Doing so prevents the program counter from being loaded with data memory instead of an opcode from the program memory ...
Page 96
... ADE7566/ADE7569 ECON—Flash/EE Memory Control SFR Programming flash memory is done through the Flash Control SFR (ECON, 0xB9). This SFR allows the user to read, write, erase, or verify the flash memory method of security, a key must be written to the FLSHKY register to initiate any user access to the flash memory ...
Page 97
... MOV EDATA,#F3h MOV EADRH,#3Ch MOV EADRL,#00h MOV FLSHKY,#3Bh key. MOV ECON,#05h ; Erase page and then write byte Rev Page 97 of 136 ADE7566/ADE7569 PROTR.3 PROTR.2 PROTR.1 Page 12 to Page 8 to Page 4 to Page 15 Page 11 Page 7 EADRL ...
Page 98
... ADE7566/ADE7569 PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected are not able to be read by the end user. The write protection ensures that the flash memory cannot be erased or written over ...
Page 99
... Protection configured in the last page of the ADE7566/ADE7569 affects whether flash memory can be accessed in serial download mode. Read protected pages cannot be read. Write/erase protected pages cannot be written or erased ...
Page 100
... ADE7566/ADE7569 TIMERS Each ADE7566/ADE7569 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx ( 2). All three can be configured to operate either as timers or as event counters ...
Page 101
... Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Rev Page 101 of 136 ADE7566/ADE7569 ...
Page 102
... ADE7566/ADE7569 Table 104. Timer 0 High Byte SFR (TH0, 0x8C) Bit No. Mnemonic Default Description TH0 0 Timer 0 Data High Byte. Table 105. Timer 0 Low Byte SFR (TL0, 0x8A) Bit No. Mnemonic Default Description TL0 0 Timer 0 Data High Byte. Table 106. Timer 1 High Byte SFR (TH1, 0x8D) Bit No ...
Page 103
... In this mode, the EXF2 flag can, however, still cause interrupts that can be used as a third external interrupt. Baud rate generation is described as part of the UART serial port operation in the UART Serial Interface section. Rev Page 103 of 136 ADE7566/ADE7569 CAP2 TR2 Mode 0 ...
Page 104
... ADE7566/ADE7569 f CORE P1.4/T2 TRANSITION DETECTOR P1.3/ T2EX f CORE P1.4/T2 TRANSITION DETECTOR P1.3/ T2EX TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL EXEN2 Figure 94. Timer/Counter 2, 16-Bit Autoreload Mode TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 CAPTURE RCAP2L RCAP2H CONTROL EXEN2 Figure 95. Timer/Counter 2, 16-Bit Capture Mode Rev ...
Page 105
... PLL The ADE7566/ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power savings when maximum core performance is not required. ...
Page 106
... ADE7566/ADE7569 Table 115. Peripheral Configuration SFR (PERIPH, 0xF4) Bit No. Mnemonic Default 7 RXFLAG 0 6 VSWSOURCE 1 5 VDD_OK 0 4 PLL_FLT 0 3 REF_BAT_EN 0 2 Reserved RXPROG[1:0] 00 Table 116. Start ADC Measurement SFR (ADCGO, 0xD8) Bit No. Address Mnemonic 7 0xDF PLL_FTL_ACK 0xDE to 0xDB ...
Page 107
... REAL TIME CLOCK The ADE7566/ADE7569 have an embedded real time clock (RTC) as shown in Figure 96. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is maintained active in all power saving modes ...
Page 108
... ADE7566/ADE7569 Table 118. RTC Configuration SFR (TIMECON, 0xA1) Bit No. Mnemonic Default Description 7 MIDNIGHT 0 Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is raised once a day at midnight ...
Page 109
... Result (Calibration Window, Frequency) 0 30.5 sec 30.5 sec, 512 Hz 0 0.244 sec, 500 Hz 1 0.244 sec, 16.384 kHz Result 0 0 GPIO 0 1 BCTRL 1 x INT1 input disabled 1 x INT1 input enabled Result INT0 input disabled INT0 input enabled Rev Page 109 of 136 ADE7566/ADE7569 ...
Page 110
... RTC interrupt by servicing the event and clearing the appropriate flag in the RTC interrupt servicing routine. Note that if the ADE7566/ADE7569 are awakened by an RTC event, either by the MIDNIGHT event or ALARM event, the pending RTC interrupt must be serviced before the device can go back to sleep again ...
Page 111
... RTCCOMP × During calibration, user software writes the RTC with the current time. Refer to the Read and Write Operations section for more information on how to read and write the RTC timekeeping registers. Rev Page 111 of 136 ADE7566/ADE7569 Calibration f RTCCAL Window (sec) (Hz) 30.5 1 30.5 512 0 ...
Page 112
... ADE7566/ADE7569 UART SERIAL INTERFACE The ADE7566/ADE7569 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f • 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 baud/sec and 115,200 baud/sec ...
Page 113
... Not Implemented, Write Don’t Care. UART Timer Fractional Divider Bit 5. UART Timer Fractional Divider Bit 4. UART Timer Fractional Divider Bit 3. UART Timer Fractional Divider Bit 2. UART Timer Fractional Divider Bit 1. UART Timer Fractional Divider Bit 0. Rev Page 113 of 136 ADE7566/ADE7569 Description Serial Port Data Buffer. ...
Page 114
... ADE7566/ADE7569 Table 134. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115,200 0 115,200 1 57,600 0 57,600 1 38,400 0 38,400 1 38,400 2 19,200 0 19,200 1 19,200 2 19,200 3 9600 0 9600 1 9600 2 9600 3 9600 4 4800 0 4800 1 4800 2 4800 3 4800 4 4800 5 2400 0 2400 1 2400 ...
Page 115
... If the address does not match, the device continues to listen for address packets. Rev Page 115 of 136 ADE7566/ADE7569 If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must receive a character. This ensures that the data in the SBUF SFR is not overwritten if the last received character has not been read ...
Page 116
... ADE7566/ADE7569 To transmit, the 8 data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, the 8 data bits from SBUF are loaded into the transmit shift register (LSB first) ...
Page 117
... UART is required. To address this problem, each ADE7566/ADE7569 has a dedicated baud rate timer (UART timer) specifically for generating highly accurate baud rates. The UART timer can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates, including 115,200 bps ...
Page 118
... RB8 bit is low. Break error detection is not possible for a 9-bit 8052 UART because the stop bit is not = . recorded. The ADE7566/ADE7569 enhanced break error detection is available through the BE bit in the SBAUDT SFR. The 8052 standard UART prevents overwrite errors by not ⎞ ⎟ ...
Page 119
... SERIAL PERIPHERAL INTERFACE (SPI) The ADE7566/ADE7569 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that 8 bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users to read the last byte of received data while a new byte is shifted in ...
Page 120
... ADE7566/ADE7569 Table 138. SPI Configuration SFR 1 (SPIMOD1, 0xE8) Bit No. Address Mnemonic 0xEF to 0xEE Reserved 5 0xED INTMOD 4 0xEC AUTO_SS 3 0xEB SS_EN 2 0xEA RxOFW 0xE9 to 0xE8 SPIR[1:0] Default Description 0 Reserved. 0 SPI Interrupt Mode. INTMOD Result 0 SPI interrupt set when SPI Rx buffer is full. ...
Page 121
... SPI data input is sampled at the second SCLK edge and then every two subsequent edges. Result The MSB of the SPI outputs is transmitted first. The LSB of the SPI outputs is transmitted first. Result This bit must be left set for proper operation. Rev Page 121 of 136 ADE7566/ADE7569 ...
Page 122
... ADE7566/ADE7569 Table 140. SPI Interrupt Status SFR (SPISTAT, 0xEA) Bit No. Mnemonic Default Description 7 BUSY 0 SPI Peripheral Busy Flag. BUSY MMERR 0 SPI Multimaster Error Flag. MMERR SPIRxOF 0 SPI Receive Overflow Error Flag. Reading the SPI2CRx SFR clears this bit. SPIRxOF ...
Page 123
... MOV A or SPI2CRX. Using a 3-cycle instruction such as MOV 0x3D or SPI2CRX does not transfer the right information into the target register. Transfer continues until the SPI2CTx register and transmit shift registers are empty. Rev Page 123 of 136 ADE7566/ADE7569 SS SCLK AUTO_SS = 1 SPICONT = 1 ...
Page 124
... ADE7566/ADE7569 SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double buffered receive and transmit registers. Figure 104 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the transmit shift register is loaded with ...
Page 125
... I C COMPATIBLE INTERFACE The ADE7566/ADE7569 support a fully licensed I 2 The I C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. Therefore, the user can enable only one interface or the other on these pins at any given time ...
Page 126
... ADE7566/ADE7569 2 Table 145 Interrupt Status Register SFR (SPI2CSTAT, 0xEA) Bit No. Mnemonic Default 7 I2CBUSY 0 6 I2CNOACK 0 5 I2CRxIRQ 0 4 I2CTxIRQ I2CFIFOSTAT[1: I2CACC_ERR 0 0 I2CTxWR_ERR 0 READ AND WRITE OPERATIONS 1 SCLK SDATA START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ...
Page 127
... MOV I CTx, TxDATA4 2 I CTx TxDATA4 TxDATA3 4 BYTE FIFO TxDATA2 TxDATA1 TRANSMIT SHIFT REGISTER Figure 108. I Rev Page 127 of 136 ADE7566/ADE7569 CODE TO READ Rx FIFO: 2 MOV A, I CRx; RESULT RxDATA1 2 MOV A, I CRx; RESULT RxDATA2 2 MOV A, I CRx; RESULT RxDATA3 2 MOV A, I CRx; RESULT RxDATA4 ...
Page 128
... ADE7566/ADE7569 DUAL DATA POINTERS Each ADE7566/ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR (DPCON, 0xA7). DPCON features automatic hardware post-increment and postdecrement, as well as an automatic data pointer toggle. ...
Page 129
... I/O PORTS PARALLEL I/O The ADE7566/ADE7569 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on- chip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O. The I/O port can be configured through the SFRs in Table 147 ...
Page 130
... ADE7566/ADE7569 I/O REGISTERS Table 148. Extended Port Configuration SFR (EPCFG, 0x9F) Bit No. Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 149. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) Bit No. Mnemonic 7 PINMAP0.7 6 PINMAP0.6 5 PINMAP0.5 4 PINMAP0.4 3 PINMAP0.3 2 PINMAP0.2 1 PINMAP0.1 0 PINMAP0.0 Table 150. Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3) Bit No ...
Page 131
... This bit reflects the state of P2.3/SDEN pin. It can be written only. 1 This bit reflects the state of P2.2/FP16 pin. It can be written or read. 1 This bit reflects the state of P2.1/FP17 pin. It can be written or read. 1 This bit reflects the state of P2.0/FP18 pin. It can be written or read. Rev Page 131 of 136 ADE7566/ADE7569 ...
Page 132
... ADE7566/ADE7569 Table 155. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 FP19 LCD Segment Pin P0.2 CF1 ADE Calibration Frequency Output P0.3 CF2 ADE Calibration Frequency Output P0.4 MOSI SPI Data Line ...
Page 133
... The weak internal pull-up is disabled by writing PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 157. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0. Rev Page 133 of 136 ADE7566/ADE7569 ...
Page 134
... DETERMINING THE VERSION OF THE ADE7566/ADE7569 Each ADE7566/ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7566/ADE756 version corresponding to this datasheet is ADE7566/ADE7569V3.4. To access this value, the following procedure can be followed: 1 ...
Page 135
... VIEW 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 112. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters Rev Page 135 of 136 ADE7566/ADE7569 12.20 12.00 SQ 11. 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9. 0.27 0.22 0.17 0.30 0.25 ...
Page 136
... ADE7566/ADE7569 ORDERING GUIDE di/dt Sensor 1 Model Interface 2 ADE7566ACPZF8 No 2 ADE7566ACPZF8- ADE7566ACPZF16 No 2 ADE7566ACPZF16- ADE7566ASTZF8 No 2 ADE7566ASTZF8- ADE7566ASTZF16 No 2 ADE7566ASTZF16- ADE7569ACPZF16 Yes 2 ADE7569ACPZF16-RL Yes 2 ADE7569ASTZF16 Yes 2 ADE7569ASTZF16-RL Yes EVAL- ADE7569F16EBZ 2 1 All models have rms LCD, and RTC. ...