ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 31

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, normal operating mode, V
of the analog and digital circuitry powered by V
are enabled by default. In normal mode, the default clock
frequency, f
reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
In PSM1, battery mode, V
mode, the 8052 core and all of the digital circuitry are enabled
by default. The analog circuitry for the ADE energy metering
DSP powered by V
matically restarts, and the switch to the V
when the V
in the MODE1 register (0x0B) is cleared (see Table 32). The
default f
software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, V
digital and analog circuitry powered through V
disabled, including the MCU core, resulting in the following:
Table 27. SFR Maintained in PSM2
I/O Configuration
Interrupt Pins Configuration SFR
(INTPR, 0xFF), see
Peripheral Configuration SFR
(PERIPH, 0xF4), see
Port 0 Weak Pull-Up Enable SFR
(PINMAP0, 0xB2), see
Port 1 Weak Pull-Up Enable SFR
(PINMAP1, 0xB3), see
Port 2 Weak Pull-Up Enable SFR
(PINMAP2, 0xB4), see
Scratch Pad 1 SFR (SCRATCH1, 0xFB),
see
Scratch Pad 2 SFR (SCRATCH2, 0xFC),
see
Scratch Pad 3 SFR (SCRATCH3,
0xFD), see
Scratch Pad 4 SFR (SCRATCH4, 0xFE),
see
Table 21
Table 22
Table 24
CORE
Table 23
CORE
DD
for PSM1, established during a power-on reset or
supply is above 2.75 V and when the PWRDN bit
, established during a power-on reset or software
Table 16
Table 19
INTA
Table 149
Table 150
Table 151
is disabled. This analog circuitry auto-
SW
SW
is connected to V
is connected to V
Power Supply Monitoring
Battery Detection Threshold SFR
(BATVTH, 0xFA), see
Battery Switchover Configuration
SFR (BATPR, 0xF5), see
Battery ADC Value SFR
(BATADC, 0xDF), see
Peripheral ADC Strobe Period SFR
(STRBPER, 0xF9), see
Temperature and Supply Delta SFR
(DIFFPROG, 0xF3), see
VDCIN ADC Value SFR
(VDCINADC, 0xEF), see
Temperature ADC Value SFR
(TEMPADC, 0xD7), see
SW
is connected to V
DD
power supply occurs
BAT
INTA
BAT
. In this operating
INTD
. All of the 2.5 V
and V
and V
Table 50
INTD
Table 47
Table 52
Table 18
Table 51
Table 48
Table 53
DD
INTA
are
. All
Rev. 0 | Page 31 of 136
RTC Peripherals
RTC Nominal Compensation SFR
(RTCCOMP, 0xF6), see
RTC Temperature Compensation SFR
(TEMPCAL, 0xF7), see
RTC Configuration SFR (TIMECON, 0xA1),
see
Hundredths of a Second Counter SFR
(HTHSEC, 0xA2), see
Seconds Counter SFR (SEC, 0xA3), see
Table 120
Minutes Counter SFR (MIN, 0xA4), see
Table 121
Hours Counter SFR (HOUR, 0xA5), see
Table 122
Alarm Interval SFR (INTVAL, 0xA6), see
Table 123
Table 118
•
•
The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC,
and LCD) are active in PSM2. They can be enabled or disabled
to reduce power consumption and are configured for PSM2
operation when the MCU core is active (see Table 28 for more
information about the individual peripherals and their PSM2
configuration). The ADE7566/ADE7569 remain in PSM2 until
an event occurs to wake it up.
In PSM2, the ADE7566/ADE7569 provide four scratch pad
RAM SFRs that are maintained during this mode. These SFRs
can be used to save data from PSM0 or PSM1 when entering
PSM2 (see Table 20 to Table 24).
In PSM2, the ADE7566/ADE7569 maintain some SFRs (see
Table 27). The SFRs that are not listed in this table should be
restored when the part enters PSM0 or PSM1 from PSM2.
The RAM in the MCU is no longer valid.
The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from
where it left off, but always starts from the power-on reset
vector when the ADE7566/ADE7569 exit PSM2.
Table 119
Table 125
Table 124
ADE7566/ADE7569
LCD Peripherals
LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED), see
86
LCD Configuration Y SFR
(LCDCONY, 0xB1),see
LCD Configuration X SFR
(LCDCONX, 0x9C), see
LCD Configuration SFR
(LCDCON, 0x95), see
LCD Clock SFR (LCDCLK, 0x96),
see
LCD Segment Enable SFR
(LCDSEGE, 0x97) see
LCD Pointer SFR (LCDPTR, 0xAC),
see
LCD Data SFR (LCDDAT, 0xAE),
see
Table 80
Table 84
Table 85
Table 76
Table 83
Table 79
Table 78
Table