ade7166 Analog Devices, Inc., ade7166 Datasheet - Page 118

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ade7166

Manufacturer Part Number
ade7166
Description
Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
Manufacturer
Analog Devices, Inc.
Datasheet

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ADE7566/ADE7569/ADE7166/ADE7169
Table 125. Alarm Interval SFR (INTVAL, 0xA6)
Bit
7 to 0
Table 126. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit
7 to 0
Table 127. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit
7 to 0
Table 128. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit
7
6 to 5
4
3 to 1
0
Table 129. Key SFR (KYREG, 0xC1)
Bit
7 to 0
Mnemonic
KYREG
Mnemonic
INTVAL
Mnemonic
RTCCAL
FSEL[1:0]
Reserved
INT1PRG[2:0]
INT0PRG
Mnemonic
Mnemonic
RTCCOMP
TEMPCAL
Default
0
Default
0
Default
0
Default
0
Default
0
000
0
Description
The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC to calibrate the RTC over
temperature. This allows the external crystal shift to be compensated over temperature. This register is
retained during a watchdog reset or an external reset. It is reset after a POR.
Description
Controls the RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
Sets RTC calibration output frequency and calibration window.
FSEL[1:0]
0
0
1
1
Controls the function of INT1.
INT1PRG[2:0]
x
x
0
1
Controls the function of INT0.
INT0PRG
0
1
Description
Write 0xA7 to the this SFR before writing to the POWCON SFR, which unlocks KYREG.
Write 0xEA to the this SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping
registers to unlock KYREG.
Description
The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration
SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a
pending RTC interrupt is created. Note that the interval counter is eight bits. Therefore, it can count up to
255 seconds, for example.
Description
The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. This register is retained during
a watchdog reset or an external reset. It is reset after a POR.
0
0
1
1
0
1
0
1
0
1
x
x
Rev. A | Page 118 of 144
Result (Calibration Window, Frequency)
30.5 sec, 1 Hz
30.5 sec, 512 Hz
0.244 sec, 500 Hz
0.244 sec, 16.384 kHz
Result
GPIO
BCTRL
INT1 input disabled
INT1 input enabled
Result
INT0 input disabled
INT0 input enabled

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