ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 35

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
registers. If the result is positive, 512 is added to the result
before writing it into xPHCAL.
Figure 38 illustrates how the phase compensation is used to remove
x = −1° phase lead in IA of the current channel from the external
current transducer (equivalent of 55.5 µs for 50 Hz systems). To
cancel the lead (1°) in the current channel of Phase A, a phase
REFERENCE CIRCUIT
The nominal reference voltage at the REF
0.075% V. This is the reference voltage used for the ADCs in
the ADE7880. The REF
external source, for example, an external 1.2 V reference. The
voltage of the ADE7880 reference drifts slightly with
temperature; see the Specifications section for the temperature
coefficient specification (in ppm/°C). The value of the temperature
drift varies from part to part. Because the reference is used for
all ADCs, any x% drift in the reference results in a 2x% deviation
of the meter accuracy. The reference drift resulting from
temperature changes is usually very small and typically much
smaller than the drift of other components on a meter.
Alternatively, the meter can be calibrated at multiple temperatures.
If Bit 0 (EXTREFEN) in the CONFIG2 register is cleared to 0 (the
default value), the ADE7880 uses the internal voltage reference.
If the bit is set to 1, the external voltage reference is used. Set the
APHCAL,
BPHCAL, or
CPHCAL =







phase
phase
IN/OUT
_
_
resolution
VA
resolution
x
x
IA
pin can be overdriven by an
VA
IA
VAP
IAP
IAN
VN
+
,
50Hz
1°
PGA1
PGA3
x
512
IN/OUT
≤
0
,
x
>
pin is 1.2 ±
Figure 38. Phase Calibration on Voltage Channels
0







Rev. PrE | Page 35 of 103
(8)
ADC
ADC
IA
VA
CALIBRATION
APHCAL = 57
PHASE
lead must be introduced into the corresponding voltage channel.
Using Equation 8, APHCAL is 57 least significant bits, rounded
up from 56.8. The phase lead is achieved by introducing a time
delay of 55.73 µs into the Phase A current.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE785xx work on 32-, 16-, or 8-bit words.
As shown in Figure 37, APHCAL, BPHCAL, and CPHCAL
10-bit registers are accessed as 16-bit registers with the six MSBs
padded with 0s.
CONFIG2 register during the PSM0 mode. Its value is maintained
during the PSM1, PSM2, and PSM3 power modes.
DIGITAL SIGNAL PROCESSOR
The ADE7880 contains a fixed function digital signal processor
(DSP) that computes all powers and rms values. It contains
program memory ROM and data memory RAM.
The program used for the power and rms computations is
stored in the program memory ROM and the processor executes
it every 8 kHz. The end of the computations is signaled by
setting Bit 17 (DREADY) to 1 in the STATUS0 register. An
interrupt attached to this flag can be enabled by setting Bit 17
(DREADY) in the MASK0 register. If enabled, the IRQ0 pin is
set low and Status Bit DREADY is set to 1 at the end of the
computations. The status bit is cleared and the
to high by writing to the STATUS0 register with Bit 17 (DREADY)
set to 1.
The registers used by the DSP are located in the data memory
RAM, at addresses between 0x4380 and 0x43BE. The width of
Figure 37. xPHCAL Registers Communicated As 16-Bit Registers
15
0000 00
PHASE COMPENSATION
ACHIEVED DELAYING
IA BY 56µs
10 9
xPHCAL
IRQ0 pin is set
0
ADE7880