ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 97

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
Location
15:9
Table 44. CONFIG Register (Address 0xE618)
Bit
Location
0
1
2
3
4
5
6
7
9:8
11:10
13:12
15:14
Table 45. MMODE Register (Address 0xE700)
Bit
Location
1:0
2
Bit Mnemonic
Reserved
Bit Mnemonic
INTEN
Reserved
CF2DIS
SWAP
MOD1SHORT
MOD2SHORT
HSDCEN
SWRST
VTOIA[1:0]
VTOIB[1:0]
VTOIC[1:0]
Reserved
Bit Mnemonic
Reserved
PEAKSEL[0]
Default Value
000 0000
Default Value
0
1
0
0
0
0
0
0
00
00
00
Default Value
1
Description
1: if the sum of all phase powers in the CF3 datapath is negative. Phase powers in the CF3
datapath are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by
Bits[8:6] (CF3SEL[x]) of the CFMODE register.
Reserved. These bits are always 0.
Description
This bit manages the integrators in the phase current channels.
If INTEN=0, then the integrators in the phase current channels are always disabled.
If INTEN=1, then the integrators in the phase currents channels are enabled.
The neutral current channel integrator is managed by Bit 3 (ININTEN ) of CONFIG3 register.
Reserved. This bit should be maintained at 1 for proper operation.
When this bit is cleared to 0, the CF2 functionality is chosen at CF2/HREADY pin.
When this bit is set to 1, the HREADY functionality is chosen at CF2/HREADY pin.
When this bit is set to 1, the voltage channel outputs are swapped with the current channel
outputs. Thus, the current channel information is present in the voltage channel registers
and vice versa.
When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at
CF3/HSCLK pin.
When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
When this bit is set to 1, a software reset is initiated.
These bits decide what phase voltage is considered together with Phase A current in the
power path.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIA[1:0] = 00.
These bits decide what phase voltage is considered together with Phase B current in the
power path.
00 = Phase B voltage.
01 = Phase C voltage.
10 = Phase A voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIB[1:0] = 00.
These bits decide what phase voltage is considered together with Phase C current in the
power path.
00 = Phase C voltage.
01 = Phase A voltage.
10 = Phase B voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIC[1:0] = 00.
Description
PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three
phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak
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ADE7880