ade7953 Analog Devices, Inc., ade7953 Datasheet - Page 53

no-image

ade7953

Manufacturer Part Number
ade7953
Description
Single Phase, Multifunction Metering Ic With Neutral Current Measurement Ade7953
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ade7953ACPZ
Manufacturer:
Samsung
Quantity:
7 040
Part Number:
ade7953ACPZ
Manufacturer:
ADI
Quantity:
207
Part Number:
ade7953ACPZ
Manufacturer:
ADI
Quantity:
1 263
Part Number:
ade7953ACPZ
Manufacturer:
AD
Quantity:
1 960
Part Number:
ade7953ACPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ade7953ACPZ
Quantity:
15 000
Company:
Part Number:
ade7953ACPZ
Quantity:
44
Part Number:
ade7953ACPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
I
The I
stage sets the pointer to the address of the register to be
accessed. The second stage reads the contents of the register.
As shown in Figure 71, the first stage is initiated when the
master issues a start condition, which consists of the slave
address and the read/write bit. Because this first step sets up the
pointer to the address, the LSB of the start byte should be set to
0 (write). The start condition is followed by the 16-bit address
of the target register. After each byte is received, the ADE7953
issues an acknowledge (ACK) to the master.
2
C Read Operations
S
2
C read operation is performed in two stages. The first
0
S
SLAVE ADDRESS
1
0
1
1
1
SLAVE ADDRESS
0
1
0
1
0
0
0
0
ACK GENERATED BY
C
K
A
0
15
MSB OF REGISTER ADDRESS
ADE7953
1
A
C
K
23
ACK GENERATED BY
BYTE 3 (MSB)
OF REGISTER
ADE7953
8
A
C
K
LSB OF REGISTER ADDRESS
7
16
A
C
K
15
Rev. 0 | Page 53 of 68
Figure 71. I
BYTE 2 OF REGISTER
0
A
C
K
2
C Read
ACK GENERATED BY
The second stage of the read operation begins with the master
generating a new start condition. This start condition consists of
the same slave address but with the LSB set to 1 to signify that a
read is being issued. After this byte is received, the ADE7953
issues an acknowledge (ACK). The ADE7953 then sends the
register contents to the master, which acknowledges the reception
of each byte. All bytes are sent MSB first. The register contents
can be 8, 16, 24, or 32 bits long. After the final byte of register
data is received, the master issues a stop condition in place of
the acknowledge to indicate the completion of the communication.
The I
MASTER
8
2
C read operation is shown in Figure 71.
A
C
K
7
BYTE 1 OF REGISTER
0
A
C
K
7
OF REGISTER
BYTE 0 (LSB)
ADE7953
0
P

Related parts for ade7953