ade7953 Analog Devices, Inc., ade7953 Datasheet - Page 58

• Manufacturer Part Number: ade7953
• Description: Single Phase, Multifunction Metering Ic With Neutral Current Measurement Ade7953
• Manufacturer: Analog Devices, Inc.

ADE7953
ADE7953 REGISTERS
The ADE7953 contains registers that are 8, 16, 24, and 32 bits long. All signed registers are in the twos complement format with the
exception of the PHCALA and PHCALB registers, which are in sign magnitude format. The 24-bit and 32-bit registers contain the same
data but can be accessed in two different register lengths. The 24-bit register option increases communication speed; the 32-bit register
option provides simplicity when coding with the long format. When accessing the 32-bit registers, only the lower 24 bits contain valid
data (the upper 8 bits are sign extended). A write to a 24-bit register changes the value in the corresponding 32-bit register, and vice versa.
Therefore, each 24-/32-bit register can be thought of as one memory location that can be accessed via two different paths.
Table 13. 8-Bit Registers
Address
0x000
0x001
0x004
0x007
0x008
0x009
0x040
0x0FD
0x0FF
0x702
0x800
Table 14. 16-Bit Registers
Address
0x100
0x101
0x102
0x103
0x104
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x110
0x1FE
0x1FF
Register Name
ZXTOUT
LINECYC
CONFIG
CF1DEN
CF2DEN
CFMODE
PHCALA
PHCALB
PFA
PFB
ANGLE_A
ANGLE_B
Period
ALT_OUTPUT
LAST_ADD
LAST_RWDATA
Register Name
SAGCYC
DISNOLOAD
LCYCMODE
PGA_V
PGA_IA
PGA_IB
WRITE_PROTECT
LAST_OP
LAST_RWDATA
Version
EX_REF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R/W
R
R
Default
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x00
0x00
N/A
0x00
Default
0xFFFF
0x0000
0x8004
0x003F
0x003F
0x0300
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Rev. 0 | Page 58 of 68
Type
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Type
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Signed
Signed
Signed
Signed
Signed
Signed
Unsigned
Unsigned
Unsigned
Unsigned
Register Description
Sag line cycles
No-load detection disable
Line cycle accumulation mode configuration
Voltage channel gain configuration (Bits[2:0])
Current Channel A gain configuration (Bits[2:0])
Current Channel B gain configuration (Bits[2:0])
Write protection bits (Bits[2:0])
Contains the type (read or write) of the last successful
communication (0x35 = read; 0xCA = write)
Contains the data from the last successful 8-bit register
communication
Contains the silicon version number
Reference input configuration: set to 0 for internal; set
to 1 for external
Power factor (Current Channel A)
Power factor (Current Channel B)
Register Description
Zero-crossing timeout
Number of half line cycles for line cycle energy
accumulation mode
Configuration register
CF1 frequency divider denominator
CF2 frequency divider denominator
CF output selection
Phase calibration register (Current Channel A). This
register is in sign magnitude format.
Phase calibration register (Current Channel B). This
register is in sign magnitude format.
Angle between the voltage input and the Current
Channel A input
Angle between the voltage input and the Current
Channel B input
Period register
Alternative output functions
Contains the address of the last successful
communication
Contains the data from the last successful 16-bit
register communication