ade7953 Analog Devices, Inc., ade7953 Datasheet - Page 9
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ade7953
Manufacturer Part Number
ade7953
Description
Single Phase, Multifunction Metering Ic With Neutral Current Measurement Ade7953
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADE7953.pdf
(68 pages)
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5, 6
7, 8
9, 10
11, 12
13
14
15
16
17
18
19
IAP, IAN
PULL_HIGH
VN, VP
PULL_LOW
CLKOUT
Mnemonic
ZX
RESET
VINTD
DGND
IBP, IBN
REF
VINTA
AGND
VDD
CLKIN
Description
Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can
be configured to output a range of alternative power quality signals (see the Alternative Output Functions
section).
Active Low Reset Input.
This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor.
Ground Reference for the Digital Circuitry.
Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated
with this input has a maximum gain stage of 22 (see the Analog Inputs section).
These pins should be connected to VDD for proper operation.
Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog
Inputs section).
Analog Input for Voltage Channel. This single-ended voltage input has a maximum input range of ±500 mV.
The PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section).
This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage
of 1.2 V. This pin should be decoupled with a 4.7 μF capacitor in parallel with a 100 nF ceramic capacitor.
Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit
section).
This pin should be connected to AGND for proper operation.
This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor.
Ground Reference for the Analog Circuitry.
Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within
3.3 V ± 10%. This pin should be decoupled with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.
Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel
resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the
ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of
picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for
the load capacitance requirements.
A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953.
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD.
SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB TO CONFER
MECHANICAL STRENGTH TO THE PACKAGE. DO NOT CONNECT THE
PADS TO AGND.
PULL_HIGH
RESET
VINTD
DGND
IAP
IAN
ZX
1
2
3
4
5
6
7
Figure 4. Pin Configuration
Rev. 0 | Page 9 of 68
(Not to Scale)
ADE7953
TOP VIEW
21 ZX_I
20 REVP
19 CLKOUT
18 CLKIN
17 VDD
16 AGND
15 VINTA
ADE7953