sta2064a STMicroelectronics, sta2064a Datasheet - Page 14

• Manufacturer Part Number: sta2064a
• Description: Cartesio? Family Infotainment Application Processor With Embedded Gps
• Manufacturer: STMicroelectronics

System features introduction
3.4
Table 3.
14/19
Power State
STANDBY
NORMAL
SLEEP
SLOW
DOZE
OFF
Power states
The following power states are defined:
●
●
●
●
●
●
●
●
While in NORMAL, SLOW AND STANDBY, V
between them) and cannot be changed. Also the power to the several IO groups is kept
unchanged.
In order to change the V
SLEEP, DEEP-SLEEP or BACKUP and then back to the selected state.
In order to keep the power consumption as low as possible, the target voltage mentioned in
DEEP-SLEEP is considered at 1.0V.
A dedicated FSM manages the power state transitions among NORMAL, SLOW, DOZE
AND SLEEP. All other states mentioned above are SW variants of the ones managed by the
FSM.
Table 3
Power mode states
OFF: V
retention is kept in the SDRAM
NORMAL: Each peripheral runs at its nominal speed with the possibility of turning off
all the unused peripherals (peripheral kernel clock gated)
SLOW: PLL1 bypassed. ARM and bus runs at crystal clock. PLL2 runs at its nominal
speed. PLL1 can be optionally put in power down
DOZE: It is like SLOW mode with the ARM running either at 19 MHz or 32 kHz
STANDBY: PLLs run at their nominal speed. Clocks are gated, ARM in WFI (Wait For
Interrupt) state
DEEP-SLEEP: V
clocked at 32 kHz making the wakeup possible. The context is put in the external
SDRAM while in self refresh mode. Only the V
SLEEP: It is like the DEEP-SLEEP mode, with the difference that V
also applied and all the PLLs are off (optional for PLL2)
BACKUP: It is like DEEP-SLEEP, with the difference that the context is not saved in the
external SDRAM. When coming out from Backup to any power state, the ARM core will
execute the first code instruction after 2ms from power on reset release.
32 kHz
shows the summary of the power states supported by STA2064.
off
on
on
on
on
on
dd_on
Off. Bypassed by
main oscillator
Off. Bypassed by
32 kHz
on (clk gated)
ARM in WFI
off
and V
PLL1
dd
off
on
dd
dd_on
powered off. V
are not applied (all data in the backup RAM is lost): no data
and V
Doc ID 16057 Rev 1
on (clk gated)
off (SW can
off (SW can
off (SW can
dd
take it on)
take it on)
take it on)
PLL2
values, the system has to transit to either OFF,
dd_on
off
on
powered (RTC, few GPIOs, backup RAM) and
dd_on
(typically 1.25V)
and V
ddio_on
1.2V to 1.3V
1.2V to 1.3V
1.2V to 1.3V
1.2V to 1.3V
1.2V to 1.3V
V
dd_on
off
dd
region must be powered
are the same (10% tolerance
=V
=V
=V
=V
=
Vdd_on
V
off
dd_on
dd_on
dd_on
dd_on
dd
dd
and V
1.7 to 3.6V
1.7 to 3.6V
1.7 to 3.6V
1.7 to 3.6V
1.7 to 3.6V
ddio
STA2064
IOs
off
are