z86e31 ZiLOG Semiconductor, z86e31 Datasheet - Page 55
z86e31
Manufacturer Part Number
z86e31
Description
Z8 4k Otp Microcontroller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z86E31.pdf
(64 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
z86e3108PSC
Manufacturer:
NS
Quantity:
162
Part Number:
z86e3108PSC
Manufacturer:
ZILOG
Quantity:
20 000
Company:
Part Number:
z86e3116PEG
Manufacturer:
Zilog
Quantity:
245
Company:
Part Number:
z86e3116PSC
Manufacturer:
Zilog
Quantity:
20
Company:
Part Number:
z86e3116PSC
Manufacturer:
ZILOG
Quantity:
55
Part Number:
z86e3116PSC
Manufacturer:
ZILOG
Quantity:
20 000
Company:
Part Number:
z86e3116PSG
Manufacturer:
Zilog
Quantity:
105
Part Number:
z86e3116SSCF6
Manufacturer:
ZILOG
Quantity:
20 000
Z86E30/E31/E40
Z8 4K OTP Microcontroller
EXPANDED REGISTER FILE CONTROL REGISTERS
56
PCON (FH) 00H
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
† Must Be 1 for Z86E30/E31
*
** Default setting after RESET and STOP-Mode Recovery.
Default setting after RESET.
Write Only Except Bit D7, Which is Read Only
Figure 42. STOP-Mode Recovery Register
Figure 41. Port Configuration Register
Write Only
SCLK/TCLK Divide-by-16
0 OFF
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag
0 POR*
1 Stop Recovery
Stop Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Comparator Output Port 3
0 P34, P37 Standard*
1 P34, P37 Comparator Output
0 Port 1 Open-Drain
1 Port 1 Push-Pull Active*†
0 Port 0 Open-Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*†
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
Low EMI Oscillator
0 Low EMI
1 Standard*
**
P R E L I M I N A R Y
WDTMR (F) 0F
*
D7 D6 D5 D4 D3 D2 D1 D0
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Default setting after RESET
Note: Not used in conjunction with SMR Source
Figure 44. STOP-Mode Recovery Register 2
Figure 43. Watch-Dog Timer Mode Register
Write Only
Write Only
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
WDT TAP
00
01
10
11
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
Reserved (Must be 0)
*
*
*
P25,P26,P27
INT RC OSC System Clock
80 ms
10 ms
20 ms
5 ms
*
DS97Z8X0502
2048 SCLK
128 SCLK
256 SCLK
512 SCLK
Zilog